• Journal of Semiconductors
  • Vol. 40, Issue 12, 122401 (2019)
Raheela Rasool, Najeeb-ud-Din, and G. M. Rather
Author Affiliations
  • Department of Electronics and Communication, National Institute of Technology, Srinagar, Jammu & Kashmir, India
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    DOI: 10.1088/1674-4926/40/12/122401 Cite this Article
    Raheela Rasool, Najeeb-ud-Din, G. M. Rather. Analytical model for the effects of the variation of ferrolectric material parameters on the minimum subthreshold swing in negative capacitance capacitor[J]. Journal of Semiconductors, 2019, 40(12): 122401 Copy Citation Text show less

    Abstract

    In this paper, we analytically study the relationship between the coercive field, remnant polarization and the thickness of a ferroelectric material, required for the minimum subthreshold swing in a negative capacitance capacitor. The interdependence of the ferroelectric material properties shown in this study is defined by the capacitance matching conditions in the subthreshold region in an NC capacitor. In this paper, we propose an analytical model to find the optimal ferroelectric thickness and channel doping to achieve a minimum subthreshold swing, due to a particular ferroelectric material. Our results have been validated against the numerical and experimental results already available in the literature. Furthermore, we obtain the minimum possible subthreshold swing for different ferroelectric materials used in the gate stack of an NC-FET in the context of a manufacturable semiconductor technology. Our results are presented in the form of a table, which shows the calculated channel doping, ferroelectric thickness and minimum subthreshold for five different ferroelectric materials.

    1. Introduction

    Negative capacitance field effect transistor (NC-FET) was proposed in 2008 by Salahuddin et al.[1] to improve the subthreshold slope of the MOSFET. It has been experimentally proven by Asif et al. in Ref. [2]. Although many technologies[3, 4] before it were suggested to improve the subthreshold slope of the MOSFET, they had inherent disadvantages that first had to be overcome. The NC-FET reduces subthreshold swing (SS) below Boltzmann's limit, due to the use of ferroelectric materials. The negative capacitance property of these materials, which actually reduces the SS, is entirely material and process dependent as described in phenomenological Landau-Devonshire theory[5]. In an NC-FET, any ferroelectric material needs to be integrated directly within the gate stack of a conventional CMOS device and its properties determine the characteristics of the device. These materials are highly process and temperature dependent, and they can switch their properties from one state to another under certain conditions. The coercive field (EC) and remnant polarization (P0) of the material and process temperature determine the Landau parameters in Landau-Khalatnikov (LK)[6, 7] equation described in the theory part of the paper.

    In this paper, we have obtained an analytical equation to determine the thickness of the ferroelectric material required to get minimum subthreshold swing, under capacitance matching condition. The limit on minimum possible subthreshold swing (Smin) reflects the choice of underlying MOS capacitance (CMOS) and ferroelectric capacitance (CFE), which is fundamentally dictated by the need to stabilise the total NC capacitor capacitance. In section 2, we describe the fundamental capacitance constraints that define the minimum subthreshold swing in an NC capacitor. In section 3, we determine the optimal thickness of the ferroelectric material and substrate doping required to observe the NC effect for a minimum subthreshold swing. In section 4, we discussed the dependence of ferroelectric thickness on the coercive field and remnant polarization. Finally, in section 5 we obtain the equation for Smin and corresponding Smin for five different ferroelectric materials.

    2. Fundamental considerations

    For the analytical analysis of our model, we have considered a basic MOS capacitor with an extra ferroelectric layer in the gate stack. A schematic of a Metal-Ferroelectric-Metal-Insulator-Substrate (MFMIS) negative capacitance capacitor[8] and its corresponding capacitance equivalent formed between the ferroelectric and the dielectric layer is shown in Figs. 1(a) and 1(b), respectively. The VGS is the applied gate voltage and VGMOS is the internal node voltage formed between the ferroelectric and the dielectric layer. Because our study examines the properties of a ferroelectric layer, we are not going to examine the electrical characteristics of the NC-FET and will instead limit our study to the capacitor only. The subthreshold swing (SS) of a MOSFET device is defined as the change in gate voltage (VGS) required to change the drain current (ID) by one order of magnitude[9]. For the negative capacitance MOS capacitor equivalent shown in Fig. 1(b), SS is given as[9]

    (a) Schematic of MFMIS based NC-FET. (b) Equivalent capacitance divider.

    Figure 1.(a) Schematic of MFMIS based NC-FET. (b) Equivalent capacitance divider.

    $ {\rm{SS}} \equiv \frac{{\partial {V_{{\rm{GS}}}}}}{{\partial \left( {{\rm{lo}}{{\rm{g}}_{10}}{I_{\rm{D}}}} \right)}} = \frac{{\partial {V_{{\rm{GS}}}}}}{{\partial {V_{{\rm{GMOS}}}}}} \times \frac{{\partial {V_{{\rm{GMOS}}}}}}{{\partial \left( {{\rm{lo}}{{\rm{g}}_{10}}{I_{\rm{D}}}} \right)}} = m \times n. $  (1)

    The SS can be reduced by reducing any of the two m or n factors. In the case of the NC capacitor, we are only concerned with the reduction of m to decrease the SS. The factor, (kB is Boltzmann's constant, T is temperature and q is electron charge) is known as transport factor and is ≈ 60 mV/decade at room temperature.

    The unique property of NC effect in an MFMIS structure is to provide an internal voltage (VGMOS) that is greater than the applied gate voltage (VGS). From the capacitor divider formed in Fig. 1(b), the partial derivative of the VGS with respect to VGMOS, also known as body factor m, can be written as

    $ m = \frac{{\partial {V_{{\rm{GS}}}}}}{{\partial {V_{{\rm{GMOS}}}}}} = {1 + \frac{{{C_{{\rm{MOS}}}}}}{{{C_{{\rm{FE}}}}}}} , $  (2)

    where is the series sum of substrate capacitance (CS) and oxide capacitance (COX) capacitances.

    To include the model for the dynamics of ferroelectric capacitor, the Landau Khalatnikov (LK) equation[6, 7] that describes the correlation between the polarization and the electric field in a single domain ferroelectric material is employed. The voltage drop across the ferroelectric layer is given as

    $ E = \frac{{{V_{\rm FE}}\left( Q \right)}}{{{t_{\rm FE}}}} = 2\alpha Q + 4\beta {Q^3} + 6\gamma {Q^5}, $  (3)

    where α, β, γ are known as Landau parameters of the material. Furthermore, α < 0, β > 0, γ ≥ 0 defines the negative capacitance property, VFE is the voltage drop across the ferroelectric film and tFE is the thickness of the ferroelectric layer. The total charge Q is the same as the total charge in the channel, which is calculated using the depletion width approximation and has already explained in Ref. [10]. The potential balance in the equivalent capacitor network results in applied gate voltage VGS as the sum of the voltage drop across the ferroelectric capacitor (VFE) and the internal node voltage VGMOS is given as

    $ {V_{{\rm{GS}}}} = {V_{{\rm{FE}}}} + {V_{{\rm{GMOS}}}}, $  (4)

    where and where VFB is the flatband voltage, VOX is the voltage across the oxide layer between ferroelectric and silicon substrate and ψS is the surface potential or band bending in the semiconductor. The capacitance CFE is the differential capacitance of ferroelectric layer and is defined . From the LK equation described in Eq. (3), the inverse of CFE is obtained as

    $ C_{{\rm{FE}}}^{ - 1}\left( Q \right) = \left( {2\alpha + 12\beta {Q^2} + 30\gamma {Q^4}} \right) {t_{{\rm{FE}}}}. $  (5)

    The total gate capacitance CT of the NC capacitor is given by

    $ C_{\rm{T}}^{ - 1}\left( Q \right) = C_{{\rm{MOS}}}^{ - 1}\left( Q \right) + C_{{\rm{FE}}}^{ - 1}\left( Q \right). $  (6)

    The increased gate capacitance due to CFE of the ferroelectric layer in the gate stack, amplifies the internal node voltage. However, CT must be positive for all charges for a hysteresis free stable operation of the device[1113]. This stability requirement puts a fundamental constraint on CMOS; i.e.,

    $ {C_{{\rm{MOS}}}}{\left( Q \right)^{ - 1}} \geqslant |{C_{{\rm{FE}}}}^{ - 1}\left( Q \right)|, $  (7)

    which should hold throughout the NC regime. Eq. (7) puts a minimum limit on the subthreshold swing that can be obtained in an NC-FET. For a given dependence of CMOS and CFE on Q, minimum SS can be obtained where the two capacitances match as closely as possible[12, 14]. However, the two cannot be made equal because they have different dependence on the value of Q and it is not possible to obtain the same values for all of the values of Q.

    For a fixed COX, CMOS changes with CS which depend on the channel doping NA; however, CS depends on whether the channel is in subthreshold, where , or in inversion, where .

    Unlike conventional MOSFETs, where the minimum value of SS is fixed at 60 mV/dec, there is no such single value in NC-FET. The minimum subthreshold swing (Smin) that characterizes the NC-FET is different for different devices. However, the two necessary conditions for minimum subthreshold swing are a) and b) channel should be in subthreshold throughout the NC regime[15] remain the same.

    Mathematically, the condition for being in subthreshold is given by (where is the surface potential, is the built-in potential on p-substrate, NA is the substrate doping and ni is the intrinsic carrier concentration), throughout the NC-regime. For uniform substrate doping and the partially depleted case, is related to the depletion charge Q by[9]

    $ {\psi _{\rm{S}}} = \frac{{{Q^2}}}{{2q{\varepsilon _0}{\varepsilon _{\rm{s}}}{N_{\rm A}}}}, $  (8)

    where is the permittivity of free space and is the permittivity of silicon substrate. The condition for subthreshold region translates Eq. (8) into , where l < 2.

    Condition (7) is general and will work irrespective of values of CMOS and |CFE|. However, Eq. (8) changes as we change the FET structure, such as single gate versus multigate[16] or bulk FET versus depleted FET.

    3. Optimal ferroelectric thickness

    Fig. 2 shows the VFEQ characteristics of the ferroelectric material. VFE decreases in the range of –Q1 < Q < + Q1 and hence CFE is also negative between –Q1 and + Q1. However, an n-channel NC-FET must be operated in the Q > 0 branch of the NC regime, so that it can be balanced by the negative charges of the channel. Therefore, is defined as the other boundary of the negative capacitance regime. At , Eq. (4) reduces to and at flatband capacitance of the underlying MOS capacitance is given by[17]

    Voltage-charge plot for a ferroelectric material.

    Figure 2.Voltage-charge plot for a ferroelectric material.

    $ \frac{1}{{{C_{{\rm{MOS}}}}}} = \sqrt {\frac{{{v_{\rm{t}}}}}{{q{\varepsilon _0}{\varepsilon _{\rm{s}}}{N_{\rm{A}}}}}} + \frac{1}{{{C_{{\rm{OX}}}}}}, $  (9)

    where vt = KBT/q is the thermal voltage. Therefore, the condition in Eq. (7) for minimum subthreshold swing and hysteresis free operation of the device can be translated into

    $ {t_{{\rm{FE}}}} = - \frac{1}{{2\alpha }}\left[ {\frac{1}{{{C_{{\rm{OX}}}}}} + \sqrt {\frac{{{v_{\rm{t}}}}}{{q{\varepsilon _0}{\varepsilon _{\rm{s}}}{N_{\rm{A}}}}}} } \right], $  (10)

    which relates tFE, and NA for minimum subthreshold slope. In addition, Q1 is the maximum charge value and Eq. (8) becomes

    $ {N_{\rm{A}}} = \frac{{Q_1^2}}{{2q{\varepsilon _0}{\varepsilon _{\rm{s}}}l{\psi _{\rm{B}}}}}. $  (11)

    The final equation for the optimized ferroelectric thickness is

    ${t_{{\rm{FE}}}} = - \frac{1}{{2\alpha }}\left[ {\frac{1}{{{C_{{\rm{OX}}}}}} + \sqrt {\frac{{2{v_{\rm{t}}}2{\psi _{\rm{B}}}}}{{Q_1^2}}} } \right]. $  (12)

    Thus, for a given ferroelectric material characterized by α, β, and γ, SS is minimized for NA and tFE given by Eqs. (11) and (12). It is clear from this equation that the thickness of ferroelectric material required depends on the landau parameter α of the material and the capacitance of the oxide between the ferroelectric and the silicon substrate. It is evident that high value of parameter α reduces the optimal ferroelectric thickness for a minimum subthreshold swing.

    4. Dependence on coercive field (EC) and remnant polarization (P0)

    The anisotropy constants α and β in Landau equation are calculated by fitting the QVFE characteristics to yield the given value of coercive field EC and the remnant polarization P0. Hence, and . Consequently, the equation for α and β becomes

    $\alpha = \frac{{3\sqrt 3 }}{4}\frac{{{E_{\rm{c}}}}}{{{P_0}}},\;\;\beta = \frac{{3\sqrt 3 }}{8}\frac{{{E_{\rm{c}}}}}{{P_0^3}}. $  (13)

    Therefore, the thickness of the ferroelectric film in terms of coercive field and remnant polarization can be obtained as

    $ {t_{{\rm{FE}}}} = \frac{2}{{3\sqrt 3 }}\frac{{{P_0}}}{{{E_{\rm{c}}}}}\left( {\frac{1}{{{C_{{\rm{OX}}}}}} + \sqrt {\frac{{2{v_{\rm{t}}}2{\psi _{\rm{B}}}}}{{Q_1^2}}} } \right), $  (14)

    the high coercive field and small remnant polarization results in small tFE.

    Ignoring the higher terms of Q in the Eq. (5), the ferroelectric negative capacitance equation reduces to

    $ {C_{{\rm{FE}}}} = \frac{1}{{2\alpha {t_{{\rm{FE}}}}}} = - \frac{2}{{3\sqrt 3 }}\frac{{{P_0}}}{{{E_{\rm{C}}}{t_{{\rm{FE}}}}}}. $  (15)

    In an NCFET device, the improved ION/IOFF ratio and small subthreshold swing without hysteresis in the transfer characteristics depends on the capacitance matching (|CFE| > CMOS) or |CFE| ≈ CMOS as already discussed[12, 13]. For the best results, |CFE| should be as close as possible to CMOS, or should be higher than the CMOS. Based on the values of NA and tFE obtained for the material PZT, CMOS and |CFE| shown in Fig. 3(a), suggesting |CFE(Q)| ≥ CMOS(Q) at each Q, as in the numerical simulation for the same material in the MFIS capacitor[18]. The corresponding VFE and VGMOS obtained from numerical simulations of MFMIS capacitor are shown in Fig. 3(b). It is clear that with the increase in Q, VFE decreases and this in turn amplifies VGMOS, and reduces SS below Boltzmann's limit of 60 mV/dec.

    (a) Capacitance versus charge plots for MOS capacitor, ferroelectric capacitor and the total capacitance of MFMIS capacitor. (b) Voltage charge plot of the MFMIS capacitor.

    Figure 3.(a) Capacitance versus charge plots for MOS capacitor, ferroelectric capacitor and the total capacitance of MFMIS capacitor. (b) Voltage charge plot of the MFMIS capacitor.

    The higher values of CFE due to smaller alpha is due to small EC and large P0 for fixed ferroelectric thickness, which results in lower voltage step up . Therefore, the gain reduces and consequently ION decreases. Although an increase in P0 reduces the hysteresis due to positive total gate capacitance, it comes at the cost of reduction in ION/IOFF which renders ineffective the primary advantage of using ferroelectric in gate stack[19].

    Similarly, high values of α implies a proportionally low value of |CFE| for a fixed tFE. This can also be understood in terms of very high coercive field and low remnant polarization. The higher values of αresults in the smaller |CFE| than CMOS, results in total negative capacitance which appears as the hysteresis in the transfer characteristics of the devices[20]. Therefore, a high coercive field improves the ION/IOFF ratio; however, hysteresis occurs in the characteristics due to instability.

    Consequently, we come to the conclusion that in an NC capacitor using ferroelectric material, the material parameters and the thickness of the material are interdependent to achieving a good result.

    Considering Eq. (14), a high P0 and low EC results in higher tFE; whereas, a low P0 and high EC results in smaller tFE. The calculated values of tFE can be used to stabilise the capacitance and enhance the capacitance matching to the obtain the best possible results with high ION and no hysteresis. Therefore, we can opt for either higher polarization and smaller EC or higher EC with smaller P0. However, from the design perspective of the NC-FET as experimentally shown in Ref. [20], the gate stack with ferroelectric material giving high EC and low P0 resulted in 45% higher ION with the same OFF current. Therefore, we can say that higher alpha and consequently lower tFE results in better characteristics and are also viable from the point of view of scaling these devices.

    5. Equation for minimum subthreshold swing

    Unlike Smin = 60 mV/dec for classical FETs, a single Smin does not define the performance of all NCFETs; instead the stability constrained Smin depends on the choice of material system and channel type. In this section, an explicit analytical equation has been obtained to calculate the minimum possible SS (Smin) under capacitance matching conditions. From the calculated Smin for different materials, we can infer the viability of different materials for the designing of NC-FETs.

    For a given ferroelectric material characterised by α, β and γ subthreshold swing is minimized for NA and tFE given in Eqs. (11) and (12). The equation for minimum subthreshold swing (Smin) is obtained by substituting the value of CFE in Eq. (2) and can be written as

    $ {S_{{\rm{min}}}} \approx \frac{{2.3{k_{\rm{B}}}T}}{q}\left( {1 + M \times {t_{{\rm{FE}}}}} \right), $  (16)

    where is a material dependent constant. The values of calculated optimal thicknesses and corresponding Smin for the five different ferroelectric materials viz: lead zirconium titanate (PZT), strontium barium titanate (SBT), barium titanate (BaTiO3), hafnium silicate (HfSiO) and organic ferroelectric material P(VDF-TrFE) are given in Table 1. The non-ideal effects (such as domain propagation, grain boundaries and domain nucleation of the ferroelectric material) degrade the subthreshold swing of the realistic device and, therefore, the minimum subthreshold swing (Smin) in Eq. (16) can be obtained when we assume that the all these non-idealities are absent[21]. The value of Smin for PZT material is 52.8 mV/dec using the above equation, which is consistent with the simulated value of 55 mV/dec for the same material by Ref. [23]. Furthermore, the value of 27 mV/dec for the organic ferroelectric material PVDF is in agreement with low SS values for such materials, as described in Ref. [24].

    Table Infomation Is Not Enable

    6. Conclusion

    In this paper, we have developed an analytical equation for the ferroelectric thickness and the minimum subthreshold swing possible in an MFMIS capacitor. This captures the impact of ferroelectric material properties on the Landau coefficients, which in turn determines the thickness of the ferroelectric material required to have better capacitance matching and which reduces the subthreshold swing. Finally, this study calculated the minimum subthreshold swing of an NC capacitor with five different ferroelectric materials, which may help us in the selection of a particular ferroelectric material for an actual NC-FET design.

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    Raheela Rasool, Najeeb-ud-Din, G. M. Rather. Analytical model for the effects of the variation of ferrolectric material parameters on the minimum subthreshold swing in negative capacitance capacitor[J]. Journal of Semiconductors, 2019, 40(12): 122401
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