Fig. 1. (Color online) Schematic cross-sectional views of the MOSFETs. (a) Planar MOSFET. (b) SG-MOSFET. (c) CIMOSFET. (d) SG-CIMOSFET.

Fig. 2. (Color online) (a) E_OX and R_ON changes of the planar MOSFET according to the W_JFET, and (b) influence of the L_split on BV, R_ON, Q_GD and E_OX in SG-MOSFET. BV is extracted at V_GS = 0 V and I_DS = 1 μA/cm².

Fig. 3. (Color online) Electron current density distribution when breakdown occurs in the SG-MOSFET (a) when L_split = 0.5 μm, and (b) when L_split = 0.6 μm.

Fig. 4. (Color online) (a) R_ON and BV relation in the SG-CIMOSFET according to change in W_P and H_P. (b)–(d) Impact ionization position when breakdown occurs in the SG-CIMOSFET according to change in W_P and H_P (the arrow indicates the breakdown point).

Fig. 5. (a) E_OX changes and (b) Q_GD changes in the SG-CIMOSFET according to change in W_P and H_P. E_OX is obtained at V_DS = 3000 V and V_GS = 0 V.

Fig. 6. The I–V characteristics of the four devices. R_ON and saturation current is obtained for V_GS = 20 V. BV is extracted at V_GS = 0 V and I_DS = 1 μA/cm².

Fig. 7. (Color online) Off-state electric field distributions of the four devices when V_GS = 0 V and V_DS = 3000 V.

Fig. 8. (Color online) The band diagram in the channel of the four devices at V_DS = 0 V, V_DS = 3000 V in off-state.

Fig. 9. (Color online) (a) Reverse transfer capacitance characteristics (C_RSS) of the five devices. (b) Input capacitance (C_ISS) and drain source capacitance (C_DS) characteristics of the five devices (when V_GS = 0 V, AC signal of 1 MHz).

Fig. 10. (Color online) (a) Depletion lines and reverse transfer capacitance models of the five devices when V_DS = 0 V, V_GS = 0 V. (b) Depletion lines of the five devices when V_DS = 800 V, V_GS = 0 V. The solid black line represents the depletion layer.

Fig. 11. Gate charge characteristics and test circuit of the four devices.

Fig. 12. Switching waveforms of the four devices. The active areas of all DUT are set to 1 cm².

Fig. 13. (Color online) (a) Double pulse test circuit. (b) Switching energy loss diagrams of the four devices.

Fig. 14. (Color online) Proposed fabrication procedure of SG-CIMSOFET. (a) N-type epitaxial growth. (b) Form the base and N⁺ source region. (c) Form the P⁺ base and central implant region by tilt ion implantation. (d) Thermal oxidation. (e) Polysilicon deposition. (f) Polysilicon etching. (g) ILD oxide deposition and contact hole etching. (h) Metallization to form the source and drain.

Table 1. Device characteristics comparison.

Table 2. Switching characteristics comparison.