Silicon carbide (SiC) is considered to be a promising candidate for power applications, thanks to its superior material properties^[1]. In particular, the SiC MOSFET has been proven to have lower switching time and loss compared to the Si insulated-gate bipolar transistor (IGBT)^[2-4]. Recently, many studies on the SiC trench MOSFET have been conducted to achieve small cell pitches and high channel mobility. Rohm proposed a double-trench MOSFET that applies a grounded p⁺ region in the source region to disperse the electric field and achieve low on-resistance (R_ON)^{[5, 6]}. However, a high electric field at the trench corner may lead to a reliability problem, which in turn makes it difficult to meet the required 3 MV/cm oxide reliability limit^[7]. In the 3.3 kV class, this problem becomes more pronounced and the channel resistance does not have a significant effect on the overall resistance due to the thick drift region. Compared to the trench MOSFETs, the simpler fabrication process and lower reverse transfer capacitance (C_RSS) of the planar MOSFETs are more suitable for high voltage (3.3 kV or larger) and fast switching applications.

There are many approaches to reduce the C_RSS (or Q_GD) in planar MOSFETs. The most widely known structure is the split gate MOSFET (SG-MOSFET), which splits the gate polysilicon to reduce the gate oxide capacitance (C_OX). The SG-MOSFET not only has inferior static characteristics compared to that of the planar MOSFET, but also has a problem that the electric field is concentrated in the gate corner. As a result, the concentrated electric field concentrated at the gate corner can lead to punch through problems^[8]. To resolve these issues, various structures using the split gate concept have been studied. Agarwal et al.^[9] successfully manufactured a 2.3 kV class SG-MOSFET, but failed to meet the 3 MV/cm limit. Han et al.^[10] proposed a buffered-gate MOSFET (BG-MOSFET) to lower the oxide field. However, the BG-MOSFET features a long cell pitch and high R_ON. Vudumula et al.^[11] obtained dramatic reduction in the C_RSS by introducing a shorted-dummy gate between the split gates. Although the shielding effect of the dummy gate led to an increased breakdown voltage (BV), the depletion region caused by the dummy gate led to a higher R_ON compared to that of a typical SG-MOSFET. Cree reported a central implant MOSFET (CIMOSFET) in which a p-type implant region was introduced in the middle of the JFET region of a planar MOSFET^{[12, 13]}. The CIMOSFET can significantly reduce the gate oxide field and C_RSS by introducing a grounded central implant region. Furthermore, by increasing the drift concentration they were able to achieve a lower R_ON compared to that of a planar MOSFET. However, the grounded central implant region of the CIMOSFET may increase the parasitic input capacitance (C_ISS) and negatively affect the switching time. Therefore, it seems very difficult to improve both static and switching performance in the SG-MOSFET. Moreover, research on the SG-MOSFET structure has only been studied up to the 2.3 kV class, and it is not clear whether the split gate concept can be applied to the 3.3 kV class.

A novel 3.3 kV split gate MOSFET with a central implant region (SG-CIMOSFET) is proposed and analyzed in comparison with the planar MOSFET, SG-MOSFET and CIMOSFET. Because of the high drain bias voltage in the 3.3 kV class, the SG-MOSFET does not guarantee the 3 MV/cm oxide limit. In addition, the SG-MOSFET suffers from issues such as punch through and drain-induced barrier lowering (DIBL), which make it more difficult to design. However, the SG-CIMOSFET blocks the oxide electric field by introducing a central implant region in the JFET region and resolves all these issues of the SG-MOSFET. Like the CIMOSFET, the SG-CIMOSFET can significantly reduce the R_ON because of the high drift doping concentration. By applying the split gate structure and grounded central implant region, the C_OX and bulk depletion capacitance (C_dep) of the SG-CIMOSFET are reduced simultaneously. In addition, the grounded central implant region partially screens the gate-to-drain capacitive coupling as seen in the CIMOSFET, resulting in the lowest C_RSS in spite of the high drift concentration. Since the gate is not directly in contact with the central implant region, the C_ISS can be reduced significantly compared to that of the CIMOSFET. As a result, the SG-CIMOSFET has the best high frequency figure of merit (HF-FOM) in terms of R_ON×Q_GD, R_ON×C_RSS, R_ON×Q_G and achieving a superior switching time as well as switching loss. Thus, the SG-CIMOSFET boasts a superior trade-off between static and switching performance.

This study was conducted by the Sentaurus TCAD tool^[14]. The electron/hole continuity equations and the Poisson equations were solved using doping-dependent Shockley–Read–Hall (SRH) recombination, Auger recombination, inversion and accumulation layer mobility models, and Okuto-Crowell models^{[15, 16]}. The mobility model contains incomplete ionization, high-field velocity saturation, and band narrowing models.

Fig. 1 shows the schematic cross-sectional views of the planar MOSFET, SG-MOSFET, CIMOSFET, and SG-CIMOSFET. In all device structures, the thickness of the 4H-SiC drift layer is 30 μm and the gate oxide thickness is 50 nm. In order to suppress the current flow disturbance resulting from the central implant region in the CIMOSFET and SG-CIMOSFET, a current spreading layer (CSL) with a doping concentration of 2 × 10¹⁶ cm^–3 is introduced in all structures. The channel length and doping concentration are 0.5 μm and 2 × 10¹⁷ cm^–3, respectively. A fixed charge concentration of 1 × 10¹² cm^–2 is included at the SiC/SiO₂ interface for all devices. In the CIMOSFET and SG-CIMOSFET, the p⁺ base and the central implant region is set to same depth to prevent additional mask consumption. The doping concentration of the central implant region is set to 5 × 10¹⁸ cm^–3.

In this optimization process, the drift concentration of all structures starts at 2.2 × 10¹⁵ cm^–3 to set BV of 3.3 kV in the planar MOSFET. Fig. 2(a) shows the maximum oxide electric field (E_OX) and R_ON changes of the planar MOSFET according to the JFET width (W_JFET). E_OX is obtained at V_DS = 3000 V and V_GS = 0 V. As the W_JFET decreases, the JFET resistance component increases significantly resulting in a high R_ON. However, a large W_JFET induces a high E_OX as it enhances the shielding ability of the p-base. Therefore, W_JFET = 2.5 μm (the cell pitch is 10 μm in all structures), which satisfies the 3 MV/cm oxide reliability limit, was adopted in the rest of the study. The relationship between the L_split and device characteristics is shown in Fig. 2(b). In Fig. 2(b), when L_split is less than 0.4 μm, E_OX is obtained when breakdown occurs because BV is less than 3000 V. As the L_split decreases so does the Q_GD. This is due to the decrease in the area between the gate and the drain. Simultaneously, the accumulation resistance increases and the field plate effect of the MOS structure decreases, leading to degradation in the R_ON and BV^{[17, 18]}. Therefore, changes in the L_split results in a trade-off between the static and dynamic characteristics. The SG-MOSFET shows a high oxide field at all L_split values due to its high drain bias voltage. Even if the gate does not protrude (when breakdown occurs at L_split = 0 μm), it shows 3.138 MV/cm of E_OX, which does not satisfy the 3 MV/cm limit. Furthermore, the electric field concentrated at the edge of the gate increases the depletion of the p-base region, which can result in punch through if it extends to the N⁺ source region. Fig. 3 shows the electron current density distribution when breakdown occurs in the SG-MOSFET. If L_split is less than 0.6 μm, premature breakdown due to punch through occurs. On the other hand, when L_split is 0.6 μm or more, the electric field is far away from the p-base and N-drift junction, and premature breakdown can be suppressed. But long L_split cannot achieve a low Q_GD compared to the planar MOSFET (210.37 nC/cm²), and the purpose of the split gate is lost. To solve this punch through problem, a long channel can be considered^[11]. However, if the channel length is increased, the V_TH, R_ON, cell pitch, and Q_GD all increase. As a result, the SG-MOSFET is not the best option in the 3.3 kV class for these given problems. The central implant region is a good solution to these problems.

Considering static and switching characteristics, the L_split = 0.3 μm was chosen for SG-CIMOSFET and SG-MOSFET in the rest of the study. Fig. 4(a) shows the R_ON and BV relation in the SG-CIMOSFET according to changes in the central implant width (W_P) and height (H_P). As W_P and H_P increase, the depletion region of the JFET region expands and the R_ON increases. However, the central implant area under the oxide disperses the electric field along with the p-base, greatly reducing the E_OX and increasing the BV. When H_P is small, the electric field dispersion effect is weak in the central implant region, and impact ionization still occurs in the p-base region (Fig. 4(b)). On the other hand, when H_P becomes large (0.6 μm or more), an excessive electric field is concentrated in the central implant region and impact ionization occurs only in the central implant region (Fig. 4(c)). When the W_P is 0.8 μm and H_P is 0.5 μm, impact ionization occurs simultaneously in the p-base and the central implant region. In this way, the highest BV (3940 V) and BV²/R_ON of 1281.88 MW/cm² were obtained as shown in Fig. 4(d). Introduction of the central implant region in the SG-CIMOSFET greatly reduces the maximum oxide field to less than 1.4 MV/cm in all the cases in Fig. 5(a). As a result, punch through is suppressed in SG-CIMOSFET. Therefore, the SG-CIMOSFET can apply a short channel length while suppressing punch through problems when compared to the SG-MOSFET. Fig. 5(b) shows the Q_GD variation with respect to W_P and H_P. As the W_P and H_P increase, Q_GD becomes smaller because of the depletion expansion. Notably, increasing W_P has a greater impact on the decrease of Q_GD than increasing H_P. This is because the grounded central implant region partially screens the capacitive coupling between the gate and the drain as W_P increases. Detailed analysis of the capacitance and gate charge characteristics will be covered in the next section. Consequently, the lowest R_ON×Q_GD of 418.17 mΩ∙nC and BV²/R_ON of 1199.79 MW/cm² were obtained for W_P = 0.8 μm and H_P = 0.6 μm. However, this study chose to move forward with W_P = 0.8 μm and H_P = 0.5 μm, which resulted in the best BV²/R_ON and had an adequately low R_ON×Q_GD of 460.18 mΩ∙nC. CIMOSFET also adopted these parameters as it resulted in the best BV²/R_ON. The CIMOSFET was almost the same BV (3949 V) as the SG-CIMOSFET. However, it has a lower R_ON (11.19 mΩ∙cm²) than the SG-CIMOSFET (12.11 mΩ∙cm²) due to its accumulation layer resistance. After parameter optimization, the BV of the SG-CIMOSFET and CIMOSFET was set to 3.3 kV by adjusting the drift doping concentration (3 × 10¹⁵ cm^–3) in order to compare the R_ON of four devices in the 3.3 kV class.

Fig. 6 shows the I–V characteristics of four devices. R_ON is obtained for V_GS = 20 V. BV is extracted at V_GS = 0 V and I_DS = 1 μA/cm². The R_ON of planar MOSFET, SG-MOSFET, CIMOSFET, and SG-CIMOSFET are 10.39, 10.49, 8.59, and 8.67 mΩ∙cm², respectively. Due to the increased drift doping concentration, CIMOSFET and SG-CIMOSFET were able to significantly improve their R_ON. Also, the SG-CIMOSFET has nearly the same R_ON as the CIMOSFET. This is because the current disturbance due to the accumulation resistance is minimized due to the improvement of the drift resistance, which occupies most of the total resistance. The off-state electric field distributions are shown in Fig. 7. Due to the split gate structure of the SG-MOSFET, the electric field is concentrated on the gate edge (E_OX = 4.56 MV/cm) and thus the 3 MV/cm reliability limit cannot be met. However, due to the introduction of the central implant region, the electric field is dispersed in the SG-CIMOSFET, reducing the E_OX by 2.5 times compared to the planar MOSFET and 4.3 times compared to the SG-MOSFET. CIMOSFET shows the lowest E_OX (0.97 MV/cm) but is not significantly different from that of the SG-CIMOSFET (1.06 MV/cm). Fig. 8 shows the band diagram in the channel of the four devices at V_DS = 0 V (solid line) and V_DS = 3000 V (dotted line). When V_DS = 0 V, the band diagram of the four devices is nearly the same because of the same p-base and CSL doping concentration. However, the SG-MOSFET and planar MOSFET show the severe barrier lowering at V_DS = 3000 V because of the potential around the channel resulting from the high electric field. The CIMOSFET and SG-CIMOSFET show excellent DIBL suppression due to the electric field shielding of the central implant region.

For the analysis of the capacitance characteristics, the SG-CIMOSFET with floating central implant region is added to understand the capacitance characteristics. Fig. 9 shows the capacitance characteristics as a function of V_DS for the five devices. The CIMOSFET has the largest C_ISS due to the overlap of the grounded central implant region and the gate. This in turn increases the switching time. In contrast, the SG-CIMOSFET shows a great reduction in C_ISS compared to the CIMOSFET, due to the separation of the central implant region and gate. In general, the C_RSS is expressed by the following equation^[8]:

$ {C_{{\rm{RSS}}}} = {\rm{}}\frac{{{C_{{\rm{ox}}}}{\rm{}} {\rm{}}{C_{{\rm{dep}}}}}}{{{C_{{\rm{ox}}}} + {C_{{\rm{dep}}}}}}, $  (1)

where C_OX is the gate oxide capacitance and C_dep is the bulk depletion capacitance. The SG-MOSFET reduces the C_RSS by reducing the C_OX. But at low V_DS, due to its shallow depletion region, the split gate structure induces a large C_dep compared to that of the planar MOSFET, as shown in Fig. 10(a)^[8]. Therefore, the C_RSS of the SG-MOSFET temporarily becomes larger than the C_RSS of the planar MOSFET in the vicinity of V_DS = 10 V, which is shown in the inset of Fig. 9(a). The CIMOSFET reduces the C_RSS in two ways. First, C_dep decreases with the expansion of the depletion region of the bulk region. Second, the grounded central implant region under the gate screens the gate-to-drain capacitive coupling^[19]. CIMOSFET has low C_RSS despite having shallow depletion regions in high V_DS (Fig. 10(b)) due to high drift doping concentration compared to SG-MOSFET and planar MOSFET. Therefore, screening the gate-to-drain capacitive coupling is the main reason for C_RSS reduction. At a low V_DS, the floating SG-CIMOSFET and SG-CIMOSFET have lower C_RSS than SG-MOSFET due to the wider depletion region by the central implant region as shown in Fig. 10(a). On the other hand, at a high V_DS, the floating SG-CIMOSFET exhibits slightly higher C_RSS than SG-MOSFET because of the large depletion region due to high drift doping concentration. But in SG-CIMOSFET, the grounded central implant region partially screens the gate-to-drain capacitive coupling like a CIMOSFET, resulting in the lowest C_RSS. Therefore, as the W_P increases, the amount of screening gate-to-drain capacitive coupling increases, resulting in a sharp decrease in Q_GD as shown in Fig. 5(b). The drain source capacitance (C_DS) characteristics of the five devices is shown in Fig. 9(b). The grounded central implant region of the CIMOSFET and SG-CIMOSFET cause an increase in C_DS. C_DS of the floating SG-CIMOSFET is larger than that of SG-MOSFET and planar MOSFET. It is due to the shallow depletion region caused by the high drift concentration. As a result, the grounded central implant region converts part of the C_RSS to C_DS and C_GS as shown in the capacitance model of the SG-CIMSOFET and the CIMOSFET (Fig. 10(a))^[20]. Increases in C_DS lead to an increase in output capacitance (C_OSS = C_DS + C_GD), which affects the reverse recovery characteristics of MOSFET due to the discharging current. However, the increase in C_DS is not insignificant, and the effect of reducing C_RSS is even greater. This further reduces the switching energy loss compared to SG-MOSFET. Detailed analysis of switching characteristics is shown in the next section.

The gate charge characteristics of the four devices are shown in Fig. 11. The mixed-mode TCAD simulation circuit is shown in the inset of Fig. 11. The Q_GD is obtained by overlaying the V_DS waveform with the gate charge characteristic (measured at 90% of the V_DS to 10% of the V_DS)^[21]. The total gate charge (Q_G) is defined as the gate charge from V_GS = 0 V to V_GS = 20 V. The Q_G, Q_GD, and Q_TH values of the four devices are shown in Table 1. The SG-CIMOSFET has the lowest Q_GD (42.49 nC/cm²) and Q_G (424.85 nC/cm²). The CIMOSFET has the second highest Q_GD (77.21 nC/cm²) but has a higher Q_G (651.56 nC/cm²) than the SG-MOSFET (503.62 nC/cm²) due to its high C_ISS. Therefore, the SG-CIMOSFET features best characteristics in terms of Q_G, Q_GD, and C_RSS. In addition, it has the smallest Q_GD/Q_TH value, which helps to suppress the parasitic turn-on effect^{[21, 22]}. The comprehensive performance of the four devices are shown in Table 1. The SG-CIMSOFET boasts the lowest HF-FOM in terms of R_ON×Q_GD, R_ON×C_RSS, and R_ON×Q_G.

The switching performance analysis of each device are conducted through a double pulse test (DPT) by the mixed-mode TCAD simulation. The active areas of all devices under test (DUT) are set to 1 cm². Fig. 12 shows the switching waveforms of the four devices. The test circuit for DPT is shown in Fig. 13(a). The body diode of the DUT was used as a freewheeling diode. The gate resistance and stray inductance are set to 20 Ω and 20 nH, respectively. The load inductor is set to 170 μH and the first V_GS pulse lasted for 10 μs to yield a load current of 100 A/cm². The gate voltage is switched between 15 and –5 V. In this paper, the turn-off time (T_OFF) consists of two parts, the turn-off delay time (T_D-OFF: from 90% of V_GS to 10% of V_DS) and the turn-off fall time (T_F: from 10% of V_DS to 90% of V_DS). The turn-on time (T_ON) consists of two parts, the turn-on delay time (T_D-ON: from 10% of V_GS to 90% of V_DS) and the turn-on rise time (T_R: from 90% of V_DS to 10% of V_DS)^[23]. Due to its low C_RSS, the SG-CIMOSFET shows the largest dV/dt, resulting in the fastest switching time in terms of T_OFF and T_ON. The CIMOSFET also shows faster T_F and T_R compared to the planar MOSFET and SG-MOSFET due to its low C_RSS. However, the CIMOSFET shows fairly slow T_D-OFF and T_D-ON due to its high C_ISS. As a result, the CIMOSFET exhibits T_OFF and T_ON similar to that of the SG-MOSFET despite its low C_RSS. Fig. 13(b) shows the switching energy loss diagrams of the four devices. Because the body diode of the DUT was used as a freewheeling diode, E_ON contains the reverse recovery energy of the DUT. It shows the E_ON of the SG-CIMSOFET is much smaller than planar MOSFET and SG-MOSFET. This means that although grounded central implant region increases the reverse recovery energy, reduction of switching energy loss because of the reduced C_RSS is more dominant in SG-CIMOSFET. The total switching energy loss (E_TOTAL) of the SG-CIMOSFET decreased by 71%, 67%, and 22%, respectively, compared to the planar MOSFET, SG-MOSFET, and CIMOSFET. The comprehensive switching performance of the four devices is shown in Table 2. SG-CIMOSFET boasts the best switching performance in terms of switching energy loss and switching time. As a result, SG-CIMOSFET can achieve a superior trade-off between static and switching performance.

Fig. 14 shows the proposed fabrication procedure of SG-CIMSOFET. After N-type epitaxial growth, the p-base and N⁺ source region can be formed by ion implantation as shown in Fig. 14(b). In Fig. 4, it shows that the static characteristics of SG-CIMOSFET according to W_P and H_P are very sensitive. To minimize the sensitivity of parameters, tilt implantation can be used to form the central implant region. The W_P and H_P can be determined by the implantation parameters^[24]. Since the P⁺ base region and the central implant region are simultaneously formed by ion implantation, it is possible to prevent additional mask consumption as shown in Fig. 14(c). The gate oxide with a thickness of 50 nm is formed by thermal oxidation. Then, polysilicon deposition and etching was carried out to form split gate structure. After ILD oxide deposition, the contact hole etching process followed to shorten the source and central implant region in Fig. 14(g)^[25]. Lastly, the metallization process followed to form the source and drain contact.

In this paper, a novel 3.3 kV class 4H-SiC SG-CIMOSFET is proposed. In the 3.3 kV class, the SG-MOSFET does not guarantee reliable operation due to its high oxide electric field. Moreover, the SG-MOSFET is very vulnerable to the punch through and has been shown to suffer from severe DIBL effect, which makes it more difficult to design devices. The SG-CIMOSFET resolves these problems by applying a central implant region and lowers the E_OX by 4.3 times compared to SG-MOSFET. Furthermore, due to its increased drift doping concentration, the SG-CIMOSFET is able to significantly improve R_ON. In addition, the SG-CIMOSFET significantly lowers the C_RSS by partially screening the gate-to-drain capacitive coupling. Compared to the planar MOSFET, the SG MOSFET and the CIMOSFET, the SG-CIMOSFET improves the R_ON×Q_GD by 83.7%, 72.4% and 44.5%, respectively. As a result, the SG-CIMOSFET shows the best performance in terms of switching energy loss and switching time. In addition to its simple fabrication process, the SG-CIMOSFET boasts superior trade-off between static and switching performance, making it a promising candidate for high voltage and high frequency applications.

This research was supported by the MSIT (Ministry of Science and ICT), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2020-2018-0-01421) supervised by the IITP (Institute for Information & communications Technology Promotion), and then Samsung Electronics.