Contact etch process optimization for RF process wafer edge yield improvement

Zhangli Liu; Bingkui He; Fei Meng; Qiang Bao; Yuhong Sun; Shaojun Sun; Guangwei Zhou; Xiuliang Cao; Haiwei Xin

doi:10.1088/1674-4926/40/12/122402

[1] B K Esfeh, M Rack, K B Ali et al. RF small- and large-signal characteristics of CPW and TFMS lines on trap-rich HR-SOI substrates. IEEE Trans Electron Devices, 65, 3120(2018).

[2] M Jaffe, M Abou-Khalil, A Botula et al. Improvements in SOI technology for RF switches. IEEE 15th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, 30(2015).

[3] F Gianesello, A Monroy, V Vialla et al. Highly linear and sub 120 fs R_on × C_off 130 nm RF SOI technology targeting 5G carrier aggregation RF switches and FEM SOC. IEEE 16th Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems (SiRF), 9(2016).

[4] C Maleville, G Celler. SOI: Challenges and solutions to increasing yield in an ultrathin age. Yield Management Solutions, 6(2004).

[5] B Delahaye, J L Baltzinger, L Denis et al. Edge and extreme edge wafer manufacturing on 200 mm wafer: methodology, yield challenges, cost effective solutions, limitations. IEEE/SEMI Advanced Semiconductor Manufacturing Conference, 100(2009).

[6] I A N Goh, H S Chua, T L Neo et al. An integrated engineering approach to improve wafer edge yield. IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings, 351(2001).

[7] K R Harris, B Y Ang. Yield implications of wafer edge engineering. International Symposium on Microelectronics & Assembly, 70(2000).

[8]

[9]

[10] Y W Men, H Zhang, K Zhou et al. Wafer back pressure control and optimization in the CMP process. J Semicond, 32, 126002(2011).

[11] J W Zhou, Y L Liu, W Zhang. Study of CMP lapping technique of ULSI silicon substrate. J Semicond, 28, 572(2007).

[12] M Boumerzoug. Optimized BARC films and etch byproduct removal for wafer edge defectivity reduction. 25th Annual SEMI Advanced Semiconductor Manufacturing Conference, 330(2014).

[13] H S Hu, M Zhang. Modeling for charging effect during RIE processing. Chin J Electron, 28, 81(2000).

[14] H T Ding, Z C Yang, G Z Yan. A dual-purpose method to enhance heat transfer and prevent notching effect in deep reactive ion etching. Chin J Electron, 38, 1201(2010).