Fig. 1. (Color online) (a) Side-view schematic illustration of a MoS₂ DG-FET. (b) Optical microscopic image of an exfoliated MoS₂ sheet on a 200-nm-thick Al₂O₃ substrate. (c) Raman spectra of MoS₂ sheets with thickness ranging from 1L to 4L. (d) Optical image of a typical 4-terminal device, the top gate electrode is relatively thin (15 nm) but still conductive. The lower graph is a schematic of the 4-terminal device in which W is the channel width and L is the distance between two inner pads. V₁ and V₂ are used to gauge the voltage drop between two inner contacts.

Fig. 2. (Color online) (a) Four-terminal conductivity σ_4prob as functions of BG, TG and DG voltages. Solid and dashed curves correspond to linear and logarithmic coordinates, respectively. (b) 2D contour plot of σ_4prob as functions of V_BG and V_TG at room temperature. (c) Mobility versus sheet thickness collected from 10 MoS₂ DG-FETs work under DG mode.

Fig. 3. (Color online) (a) With and (b) without considering quantum confinement effect, the simulation results of carrier redistribution of a 2-nm-thick MoS₂. The upper and lower panels show the simulation results from the SG (V_BG= 10 V) and DG (V_BG= V_TG= 10 V) device, respectively. (c) The electron density in the channel of the DG MoS₂ device versus channel thickness. The dielectric layer is 200 nm Al₂O_3. for all devices

Fig. 4. (Color online) Temperature dependence electrical measurement. (a) The temperature-dependent σ as a function of V_DG of a four-probe device. MoS₂ is ~5 nm thick with 200 nm Al₂O₃ of both TG and BG dielectrics. (b) The temperature-dependent mobility extracted from monolayer MoS₂ (black dot) and multi-layer MoS₂ DG-FET (red square). Monolayer MoS₂ DG-FET is 15 nm HfO₂ of both TG and BG dielectrics.