4H-SiC is a wide bandgap material with excellent material properties, such as high critical electric field, high thermal conductivity, and high-temperature operation, making it suitable for high-temperature and high-voltage environments^{[1, 2]}. In particular, high-voltage and high-frequency power devices are suitable for applications requiring high-voltage and high power density, such as the solid-state transformers used in next-generation power systems^[3]. Therefore, studies on SiC MOSFETs, which have been proven to exhibit low switching losses, are being actively conducted^[4].

Among SiC MOSFET structures, the trench MOSFET has a low channel resistance thanks to its high channel density and mobility^{[5, 6]}. However, in a high-voltage SiC MOSFET (a voltage of 3.3 kV or above), the channel resistance does not have a significant effect because of the high drift resistance. In addition, at high voltages, the trench MOSFET causes a gate oxide reliability problem in the off-state operation because the electric field is concentrated in the gate oxide^[7].

In previous studies, a central-implant MOSFET (CI-MOSFET) with a p⁺ region under the gate oxide was proposed to improve the switching characteristics of the conventional DMOSFET (C-MOSFET)^[8]. In this structure, the switching characteristics could be improved by reducing the overlapping region between the gate and the drain because of the source-contacted CI structure. However, R_ON increases because of the large depletion region formed by the PN junction in the junction gate field-effect transistor (JFET)^[9].

Therefore, we propose a 3.3 kV dummy-gate 4H-SiC MOSFET (DG-MOSFET) to alleviate this problem. The static characteristics of the DG-MOSFET were analyzed through a Sentaurus TCAD 2D simulation, and the dynamic characteristics were analyzed through a mixed-mode simulation^[10]. The power loss was compared using a PSIM simulation. In the TCAD simulation, Shockley–Read–Hall, AUGER, and Okuto–Crowell models were applied as recombination models. In addition, the doping dependence, high field velocity saturation, and Enormal were used as mobility models. To consider the device process, the trap concentration between the SiO₂ and SiC interfaces was set to 3 × 10¹² eV⁻¹ cm^−2[11-13].

Fig. 1 shows the cross-sectional schematics of the C-MOSFET, CI-MOSFET, and DG-MOSFET. All of the structures have the same drift thickness (i.e., 30 μm) and the concentration of the drift region is 1.7 × 10¹⁵ cm⁻³. The junction depth of the p base is 1 μm. In the DG-MOSFET, C_GD was reduced using the source-contacted DG structure under an active gate to reduce the overlapping region between the gate and the drain^[14]. Since the DG is a MOS structure, it has fewer depletion regions than the PN junction^[15]. Therefore, the HF-FOM is improved because C_GD can be reduced while limiting the R_ON degradation. Additionally, in the DG-MOSFET, a source contact is possible using the same method as when forming the source-contacted p⁺ shielding in the trench MOSFET^[16].

Fig. 2 shows the proposed process flow to demonstrate the feasibility of the DG-MOSFET. The p base and n⁺ sources were formed by double diffusion. After forming the nitride hard mask, it was patterned to use the hard mask for dummy etching and then the dummy area was etched. Subsequently, the SiO₂ layer is formed in the dummy region by deposition and patterning. Typically, the gate oxide is formed by thermal oxidation. However, when SiO₂ is grown by thermal oxidation, it is difficult to have the same thickness at the sidewall and bottom of the dummy region because the difference in the growth rate of SiO₂ between the sidewall and trench bottom is due to the different crystal orientation^[17]. Therefore, in the proposed structure, it was considered that the oxide in the dummy region was formed by the deposition process. After the nitride hard mask was removed, poly-Si was deposited and then etched to form poly-Si in the dummy area. The gate oxide was grown by thermal oxidation and then gate patterning was applied after the deposition of the gate poly-Si.

To analyze the performance of the proposed device, the compared devices were optimized. The CI-MOSFET and DG-MOSFET were optimized based on the C-MOSFET. The drift thickness and concentration were fixed at 30 μm and 1.7 × 10¹⁷ cm⁻³, respectively.

Fig. 3 shows the trade-off relationship between R_ON and BV based on the changes in the JFET width (W_JF) and concentration (N_JF). As shown, R_ON and BV decrease at the same time as W_JF increases. As W_JF increases, the proportion of the depletion region in the JFET decreases. Therefore, the current path increases, thus decreasing R_ON. Meanwhile, the voltage concentrated in the p⁺ region increases, which causes BV reduction. Baliga’s FOM (BV²/R_ON) was compared to optimize the C-MOSFET considering the trade-off between R_ON and BV, which is shown in Fig. 4. When W_JF is 3.5 μm, the FOM is highest at all N_JF. However, E_MOX should not exceed 4 MV/cm considering the reliability of the gate oxide^[18]. E_MOX increases with increasing N_JF, which is more remarkable with increasing W_JF. As a result, the C-MOSFET has the highest FOM when N_JF and W_JF are, respectively, 3 × 10¹⁶ cm⁻³ and 3.5 μm. In addition, E_MOX does not exceed 4 MV/cm, and BV is greater than 3300 V.

The BV, R_ON, and switching characteristics of the CI-MOSFET and DG-MOSFET are significantly affected by the CI and DG structures, respectively, existing under the gate. Therefore, the CI depth (D_CI) and width (W_CI) and the dummy depth (D_DG) and width (W_DG) were varied to optimize the two structures. As previously mentioned, both the structures were optimized based on the C-MOSFET. Therefore, W_JF and N_JF were, respectively, fixed at 10 μm and 3 × 10¹⁶ cm⁻³, which were optimized for the C-MOSFET.

Fig. 5 shows the trade-off between R_ON and BV of the CI-MOSFET when W_CI and D_CI are simultaneously varied. During the optimization process, D_CI and W_CI were varied from 0.3 to 0.9 μm and from 0.7 to 1.9 μm, respectively. In Fig. 5, at the same W_CI, R_ON increases as D_CI increases. Moreover, R_ON increases as W_CI increases at the same D_CI. This happens because the current path in the JFET decreases because of an increase in the CI region. In particular, as W_CI increases, the accumulation layer under the gate decreases, so R_ON increases rapidly. However, the CI structure causes BV to increase by dispersing the electric field concentrated in the p base. Therefore, to optimize the CI-MOSFET, it is necessary to compare the variation in the FOM based on the changes in W_CI and D_CI. In Fig. 5, BV decreases rapidly when D_CI is 0.9 μm. This happens because the electric field is concentrated in the CI structure when D_CI is too deep. This effect increases at lower W_CI. Therefore, the CI structure has the highest FOM when D_CI = 0.7 μm and W_CI = 0.7 μm as specified in Fig. 6.

The DG-MOSFET was optimized in the same way as the CI-MOSFET. Fig. 7 shows the result. The oxide thickness of the dummy region was fixed at 100 nm. As mentioned previously, the oxide in the dummy area was formed through a deposition process.

As shown in Fig. 7, D_DG and W_DG are varied from 0.3 to 0.7 μm and from 0.7 to 2.2 μm, respectively. For the same reason as that for the CI-MOSFET, an increase in the dummy area increases both R_ON and BV. Fig. 7(b) shows the variations in E_MOX and R_ON based on the changes in W_DG and D_DG. E_MOX increases when D_DG increases because of a decrease in the distance between the dummy oxide and the drain. In Fig. 8, the vertex of the dummy has the highest electric field because of the electric crowding effect. This effect is alleviated with increasing W_DG because the depletion region between the p base and the n drift protects the dummy oxide^[19]. Therefore, E_MOX is reduced when W_DG increases. However, as previously mentioned, R_ON increases significantly because of the reduction in the current path. As a result, D_DG and W_DG were optimized to 0.5 and 1.6 μm, respectively.

Based on the above results, we compared the performance of the three optimized structures. Fig. 9 shows their blocking and output characteristics. The blocking characteristics were measured at V_GS = 0 V, and the output characteristics were obtained at V_GS = 20 V. Because of the source-contacted region in the JFET, the CI-MOSFET and DG-MOSFET have 16.2% and 15.2% higher R_ON than C-MOFET, respectively. The BV values of the two structures are higher than that of the C-MOSFET because of the electric field dispersion effect. Table 1 lists the results of the static characteristics of the three optimized structures. The CI-MOSFET and DG-MOSFET have 10.4% and 11.5% lower static FOM than the C-MOSFET, respectively.

The static FOM values of the CI-MOSFET and DG-MOSFET deteriorate compared with that of the C-MOSFET. Nevertheless, both structures have improved switching characteristics. The increase in R_ON and the decrease in the switching power loss are in a trade-off relationship. Typically, R_ON is increased to reduce the switching power loss in high-frequency applications^[20].

Fig. 10 shows the input capacitance (C_ISS = C_GS + C_GD) and reverse transfer capacitance (C_RSS = C_GD) of the three structures with respect to V_DS when V_GS = 0 V^{[1, 21]}. To extract the results shown in Fig. 10, a low AC signal was applied at 1 MHz. A comparison of the C_ISS values of the three structures shows that the C_ISS values of the CI-MOSFET and DG-MOSFET are significantly higher. This can be attributed to the presence of the source-contacted region (CI and DG) under the gate. Meanwhile, the C_GD values of the CI-MOSFET and DG-MOSFET significantly decreased. C_GD is significantly influenced by the overlapping area between the gate and the drain. The DG-MOSFET can have a wider source-contacted area under the gate when it has a similar static FOM as that of the CI-MOSFET. Therefore, the DG-MOSFET has the lowest C_GD because it has the smallest overlapping area between the gate and the drain. Therefore, the DG-MOSFET has 71% and 8.3% lower C_GD than the C-MOSFET and CI-MOSFET.

Fig. 11 shows the gate charge curves of the three structures. The test circuit is specified in Fig. 11, and a current of 100 mA was applied to charge the gate. The Q_GD value of the C-MOSFET is higher than those of the CI-MOSFET and DG-MOSFET. This happens because C_GD is significantly reduced in both the structures. The HF-FOM values of the three structures were calculated and compared in Table 2. For the CI-MOSFET and DG-MOSFET, R_ON increased compared with that of C-MOSFET, but Q_GD decreased significantly. As a result, the DG-MOSFET has a 59.2% lower HF-FOM than the C-MOSFET and 22.2% lower than the CI-MOSFET.

Fig. 12 shows a diagram comparing the switching characteristics of the three structures through a double-pulse test simulation. Figs. 12(a) and 12(b) show the turn-off and turn-on transients, respectively. The test circuit is specified in Fig. 12(a), and the load inductance and stray inductance are 400 μH and 10 nH, respectively.

Consequently, the power losses in the DG-MOSFET and CI-MOSFET are significantly lower than those in the C-MOSFET. Table 3 lists the switching power loss during the double-pulse test. As listed, the DG-MOSFET has 53.4% and 5.5% lower total switching loss (E_SW) than the C-MOSFET and CI-MOSFET, respectively.

The power loss was compared using devices as switches in the power circuit through a PSIM simulation. Fig. 13 shows the buck converter and boost converter circuits used in the power loss simulation. Both circuits comprise an RLC passive device, a diode, and a switch. The L and C components help to remove the unnecessary ripple elements of the output voltage^[22]. The C-MOSFET, CI-MOSFET, and DG-MOSFET are used as switches in the power circuit. In consideration of the ideal gating block in the input gate voltage, the duty cycle was set to 0.5 and the frequency was set to 500 kHz. Finally, the output voltage was measured as the voltage of the load resistance.

Fig. 14 shows the power loss simulation results. These results are specified in Table 4. They were recorded after each circuit reached a steady state. As mentioned previously, the DG-MOSFET has the least P_SW. Consequently, when the DG-MOSFET is used as a switch, P_SW is improved by 61.9% and 12.7% compared with those of the C-MOSFET and CI-MOSFET in the buck converter. Likewise, in the boost converter, P_SW is improved by 61% and 9.6%, respectively.

In this study, a 4H-SiC DMOSFET with a source-contacted dummy gate (DG-MOSFET) was developed and compared with the C-MOSFET and CI-MOSFET through TCAD and PSIM simulations. The simulation results confirmed that the proposed DG-MOSFET structure has the least P_SW. When applied to a power circuit, this structure could save 61% and 12% P_SW in the buck converter and 61% and 9.6% P_SW in the boost converter. In particular, the DG-MOSFET exhibited a lower R_ON than the CI-MOSFET. Consequently, it exhibited a lower HF-FOM and a lower switching loss than the C-MOSFET and CI-MOSFET. Thus, it can be concluded that the proposed DG-MOSFET is more suitable for high-frequency applications.

This research was supported by the MSIT (Ministry of Science and ICT), Korea, under the ITRC (Information Technology Research Center) support program (IITP-2020-2018-0-01421) supervised by the IITP (Institute for Information & Communications Technology Planning & Evaluation).