Super-junction (SJ) technology has become a milestone in the history of power devices because it has broken the "silicon limit^"[1,2]. However, because the traditional LDMOS relies on a large cell pitch to sustain surface voltage, the benefit brought by SJ is limited. This problem is solved by the deep-trench (DT) technique, in which a DT filled with dielectric is utilized to sustain most of the surface voltage^[3-8]. However, in the Con. DT SJ LDMOS, due to the existence of the SIS capacitance, the charge balance in the SJ region is broken, which causes damage of the performance of the device^[9-12].

This paper develops a solution by adding vertical variable doping layer at the source end of the SiO₂ trench and an inverted triangular charge compensation layer at the drain end to compensate the unbalanced charge in the SJ region caused by the SIS capacitance effect on both sides of the SiO₂ dielectric trench, and optimize the surface electric field of the device. The SJ region on the source side of the DC DT SJ LDMOS is a P–N–P type super junction structure. The introduction of this P–N–P SJ structure adds a new voltage-resistant junction compared to the Con. P–N SJ structure to modulate the internal electric field and produces a new electric field peak which raises the internal electric field of the device.

The structure of the DC DT SJ LDMOS is shown asFig. 1(a).t_sj,t_drift, andt_sub represent the thickness of the SJ, the thickness of the bottom drift region and the thickness of the substrate respectively,W_sj represents the width of the super junction on both sides of the SiO₂ dielectric trench, and the width of the compensation layer is equal to the width of the SJ region.W_trench is the width of the SiO₂ dielectric trench.N_drift andN_sub are the doping concentration of the drift region at the bottom of the SiO₂ dielectric trench and the doping concentration of the substrate, respectively. The doping concentration of the P–N–P type SJ region under the source is the same,N_A1 =N_D1 =N_sj. The doping concentration of the triangle-like SJ region under the drain level is the same,N_A2 =N_D2 =N_sj2. The concentration of the triangular charge compensation layer on the left side of the SiO₂ dielectric trench isN_TB. The charge compensation layer on the right side of the SiO₂ dielectric trench is vertical variable-doped, and the doping concentration gradually decreases from the top to the bottom, which is represented byN_VB.

As can seen from theFig. 1(a), the DC DT SJ LDMOS device structure has a triangular charge compensation layer on the left side of the SiO₂ dielectric trench. The addition of the triangular charge compensation layer makes the conventional P-pillar and N-pillar SJ structure with equal width and equal concentration become a triangular-like SJ structure. The inverted triangle form of the charge compensation layer fully compensates the charge accumulated by the SIS parallel plate capacitance generated on both sides of the SiO₂ dielectric trench. The right-hand side of the SiO₂ dielectric trench adopts the P-type charge compensation layer in the form of vertical variable doping. The P-type gradient compensation layer can also fully compensate the charge generated by the SIS capacitor, and the SJ region returns to the charge balance state. The SJ region at the source side of the SiO₂ dielectric trench is a P–N–P type SJ structure. The addition of a new voltage-resistant junction improves the BV of the device in both horizontal and vertical directions. The structure of the Con. DT SJ LDMOS is shown inFig. 1(b).

The main parameters of the device structure of DC DT SJ LDMOS are shown inTable 1.

Fig. 2 shows the charge compensation principle of the DC DT SJ LDMOS. The vertical variable-doped P pillar at the source side and the inverted triangular N pillar at the drain side are used to compensate for the vertically distributed charges accumulated on both sides of the trench SiO₂ capacitor. The triangular-like SJ structure at the source side and the PNP structure at the drain side can deplete each other and maintain charge balance, so that the device reaches the charge balance.

Compared with the structure of the Con. DT SJ LDMOS device, the problem of charge imbalance due to SIS capacitance can be solved. The P–N–P type SJ structure at the source can modulate the internal electric field of the device.

The BV of DC DT SJ LDMOS has increased by 28.9% to 705.5 V. In the on-state, the current path is widen at the drain, and the doping concentration of triangular-like SJ region at the drain and P–N–P structure source is higher than that of the Con. DT SJ LDMOS so theR_on,sp can be reduced significantly.

The vertical variable-doped P-type charge compensation layer provides more uniform and sufficient charge compensation for the charge imbalance in the SJ region caused by the SIS capacitors on both sides of the SiO₂ dielectric trench. The change gradient of the vertical concentration of the P-type charge compensation layer is optimized by simulation.

The doping concentration of the P-type charge compensation layer on the right-hand side of the SiO₂ dielectric trench changes linearly. The position of the charge compensation layer is 3 to 20μm in they direction, and the thickness is 17μm. The doping concentration gradually decreased from 2 × 10¹⁵ to 1 × 10¹⁵ cm⁻³. The concentration change gradient formula is:

NVB=20−y17NVB,max+NVB,min.

This section discusses the effects ofN_D1,N_A1,N_D2,N_A2,N_drift,N_TB andN_VB on the BV,R_on,sp and FOM of the DC DT SJ LDMOS device. The above structure parameters were optimized by simulation.

Fig. 3 depicts the variation of the BV of the Con. DT SJ LDMOS and DC DT SJ LDMOS device with theN_sj at the source. It can be seen from the figure that the optimal value of the BV of the Con. DT SJ LDMOS is just 549.5 when theN_sj is 5 × 10¹⁵ cm⁻³ while the BV of the DC DT SJ LDMOS reaches a maximum of 705.5 V when theN_sj is 1.2 × 10¹⁶ cm⁻³. For the DC DT SJ LDMOS, when theN_sj ≤ 1.2 × 10¹⁶ cm⁻³, the BV increases with the N_sj. This happens because the electron-hole pairs in the device were not fully depleted and the space charge region formed by the PN junction will form an electric field spike, leading to premature breakdown of the device. After theN_sj exceeds the optimal value, the BV decreases with the increase ofN_sj, because the excess electrons or holes cannot be completely depleted, the BV begins to drop again.

Fig. 4 shows the BV and FOM of the DC DT SJ LDMOS device with the change of the triangle-like SJ doping concentrationN_sj2 at the drain side. The two curves of the device show a trend of first rising and then falling. When the concentration ofN_sj2 is 7 × 10¹⁵ cm⁻³, the BV and FOM reach the maximum. The reason of this trend is similar toFig. 3, which is related to the depletion of electron-hole pairs.

Fig. 5 shows the influence ofN_TB at the drain side on BV and FOM for the DC DT SJ LDMOS. The N-type region in the triangular SJ will not only deplete part of the charge through the SIS capacitance effect but also deplete with the P-type region. To achieve charge balance, a triangular charge compensation layer under the drain is added to compensate for holes that are not depleted in the P-type SJ region due to the SIS capacitance effect. The optimization of the doping concentrationN_TB in the triangular charge compensation layer can better solve the charge imbalance issue caused by the SIS capacitance effect. The compensation layer is an inverted triangle, which is uniformly doped, and the amount of compensation charge gradually decreases from the top to the bottom. Since the SJ region is in charge unbalanced state, which is affected by the SIS capacitance and will result in a decrease in BV.

It is very sensitive for BV that the changes in concentration of the charge compensation layer may cause a decay in its value.

It can be seen fromFig. 5 that when the triangular charge compensation layerN_TB = 5 × 10¹⁵ cm⁻³, the BV and FOM reached the maximum. Both curves show a trend of increasing first and then decreasing, when the doping concentration increases from 1 × 10¹⁵ to 5 × 10¹⁵ cm⁻³.

Fig. 6 shows how the change of vertical variable charge compensation layer doping concentrationN_VB influences BV and FOM. The doping concentration of the vertical variable doped charge compensation layer decreases with the increase ofY, and the doping concentration change is shown as Eq. (1). As shown inFig. 6, whenN_VB,min = 1 × 10¹⁵ cm⁻³ andN_VB,max = 1 × 10¹⁵ cm⁻³, the BV reaches the maximum. When the BV reaches the optimal value, the maximum concentration of the linear variable doping is 2 × 10¹⁵ cm⁻³. When the concentration of the vertical variable doping region is optimized to the optimum, the problem caused by the SIS capacitance effect in the SJ region is solved, and the SJ region returns to the charge balance state. The BV of DC DT SJ LDMOS device rises. TheR_on,sp is not affected by doping concentration. This happens because the current does not flow through the vertical variable doping P pillar. Consequently, when the BV achieves the optimal value, the FOM also achieves the optimal value.

Fig. 7 shows the influence ofN_drift on the BV and FOM of Con. DT SJ LDMOS and DC DT SJ LDMOS. From the figure it can be seen when the BV reaches the optimal value, theN_drift are 5 × 10¹⁵ and 7 × 10¹⁵ cm⁻³. TheN_drift of DC DT SJ LDMOS is higher than that of Con. DT SJ LDMOS. The N-type drift region at the bottom of the trench is mainly depleted with the P-type substrate to form a vertical P–N junction, which improves the device BV. It also serves as the necessary current path when the device is in the on state.N_drift also has great influence on theR_on,sp. It can be seen from the figure that when theN_drift = 7 × 10¹⁵ cm⁻³, the BV and FOM of the DC DT SJ LDMOS reached the maximum. After the driftN_drift reaches the optimal value, the P-type substrate is completely depleted, the BV of the DC DT SJ LDMOS device reaches the maximum value of 705.5 V.

In this part, the optimization process of key parameters that affects the performance of the device we proposed are shown as figures. In addition, the optimal value of each parameter is obtained. Compared with Con. DT SJ LDMOS, the charge imbalance problem of the Con. DT SJ LDMOS is solved by the double charge compensation layer. The electric field is modulated, and a higher BV is obtained. Compared with the Con. DT SJ LDMOS, the concentration of the drift region and SJ region of the new structure has been improved, and the conduction path is widened, which reduces theR_on,sp and achieves a much higher FOM.

The DC DT SJ LDMOS structure device with a double charge compensation layer is proposed for the problem of trench type SJ SIS capacitor in this paper. This section conducts a targeted study on the BV when the DC DT SJ LDMOS is in the off state and theR_on,sp in the on state, and compares the results of simulation to verify the principle of the device structure.

Fig. 8 shows the distribution of equipotential lines when the DC DT SJ LDMOS and Con. DT SJ LDMOS device are in the off state. Compared with the Con DT SJ LDMOS, the equipotential distribution of the new structure is denser, especially at the drain.

Fig. 9 shows the surface electric field (Y = 0.01μm) and the electric field (Y = 10μm) of the body of the DC DT SJ LDMOS device and Con. DT SJ LDMOS device in the off state. From this figure, it can be seen that the surface electric and both the surface electric field and the bulk electric field of the proposed structure are higher than those of the Con. DT SJ LDMOS. The BV of the proposed structure is also higher than that of the Con. DT SJ LDMOS.

Fig. 10 shows the breakdown characteristic curve of DC DT SJ LDMOS and Con. DT SJ LDMOS in the off state and the output characteristic curve in the on state. It can be seen from the figure that the BV of DC DT SJ LDMOS is 705.5 V, which is higer than 549.5 V of Con. DT SJ LDMOS. The illustration in theFig. 10 shows the output characteristic curves corresponding to the gate voltage 15 V of DC DT SJ LDMOS and the Con. DT SJ LDMOS respectively. It can be seen from this figure that both the on-state and off-state characteristics of the proposed structure are better than those of the Con. DT SJ LDMOS.

Fig. 11 shows the relationships between BV andR_on,sp for Con. DT SJ LDMOS, some other reported structures^[12-18] and DC DT SJ LDMOS proposed in this paper. From the figure it can be seen that the electrical performance of the device breaks through the “silicon limit”^[11].

The SIS capacitor of deep trench SJ devices leads to charge imbalance in the SJ region. The DC DT SJ LDMOS is proposed in this paper to solve this problem, which adds a vertical variable doping compensation layer on the source side and an inverted triangular charge compensation layer on the drain based on the Con. DT SJ LDMOS. Moreover, the P–N–P dual voltage-resistant junction technology is used to improve the BV of the device. The double charge compensation layer solves the problem of the charge imbalance of the SJ region caused by the SIS capacitance. The P–N–P dual voltage-resistant junction technology adjusts the internal electric field, so that the BV of the device is improved. In addition, the current path is widen by the triangular-like SJ at the drain.

The simulation results show that compared with the Con. DT SJ LDMOS, the BV increases by 28.9% to 705.5 V, and theR_on,sp of the device is reduced by 50.2% to 23.7 mΩ·cm², and the FOM reached 21.0 MW/cm².