AlGaN/GaN high-electron mobility transistors (HEMTs) or metal–insulator–semiconductor HEMTs (MIS-HEMTs), by virtue of the superior polarization-induced high mobility 2-D electron gas (2DEG), are well-proposed for their high switching speed, low parasitic parameters and low on-resistance, and have achieved recognized success in both high frequency RF and power switching applications^[1-4]. Gate- and/or source-field plates above thick passivation dielectrics like SiN_x, are commonly implemented to alleviate the high electric field in the gate-drain region and obtain higher breakdown voltage^[5–7]. They are also contributed to the suppression of surface-state-introduced current collapse^{[5, 8]}. However, the field plates structure will introduce extra parasitic capacitances, leading to higher V_DS × I_DS power loss and longer switching duration. In addition, the passivation layer will also bring in the passivation dielectric/(Al)GaN interface states and even bulk states in the dielectric itself. Their trapping/de-trapping processes cause the dynamic shifts of parasitic capacitances, leading to disordered ON-OFF transition and failure of dV/dt control in practical applications^[9–11].

In this work, gate-related parasitic capacitances of the T-shape-gate E-mode AlGaN/GaN HEMT were investigated by high-frequency C–V measurements as well as the inductive switching measurement, where C_GD was individually observed during the Miller plateau. The instability of C_GD, caused by the trapping/de-trapping of deep interface/bulk states in LPCVD-SiN_x dielectric in the gate overhang region^[12], was characterized by voltage-dependent C–V measurements.

The E-mode MIS-HEMT was fabricated on an ultra-thin-barrier (UTB) AlGaN/GaN heterostructure grown on the Si substrate^{[13, 14]}. The UTB AlGaN consists of a 1-nm AlN interlayer, a 3-nm Al_0.25Ga_0.75N barrier layer and a 1.5-nm GaN cap layer. Fig. 1(a) shows the schematic structure of the E-mode MIS-HEMT. A 10-nm LPCVD-grown SiN_x passivation layer was able to recover the 2DEG at the UTB-AlGaN/GaN interface in the access region^[15], featuring a sheet resistance of 545 Ω/□. The LPCVD-SiN_x in the gate region was etched by fluorine-based plasma. Then in-situ NH₃/N₂ remote plasma pretreatment was utilized to improve the etched (Al)GaN surface^[16], followed by the gate dielectric deposition. The gate dielectric stack consists of a 3-nm atomic layer deposited (ALD) SiN_x layer and a 15-nm ALD-Al₂O₃ layer with an ozone precursor, followed by the evaporation of a Ni/Au bilayer gate metal. The fabricated E-mode MIS-HEMT features a total gate width of 1 mm, a gate length of 1 μm, a source-to-gate spacing of 1.75 μm, and a gate-to-drain spacing of 10 μm. The T-shape gate has a 0.5 μm overhang on the source side and a 0.75 μm overhang on the drain side, as shown in Fig. 1(b).

Fig. 2(a) shows the transfer characteristics at drain bias V_DS = 1 V and V_DS = 10 V. The E-mode MIS-HEMT exhibits a threshold voltage V_TH of 1.26 V defined at I_D = 1 μA with a hysteresis of 0.3 V at V_DS = 1 V, indicating a decent ALD-SiN_x/AlGaN (F-etched) interface quantity. Fig. 2(b) shows the output characteristics. A saturation current of 339 mA is obtained at V_GS = 8 V. Fig. 2(c) shows the three-terminal off-state currents at V_GS = 0 V. A small drain leakage lower than 10^–6 mA is obtained and the gate leakage is always around 10 times lower.

Fig. 3(a) shows the schematic of the gate-related capacitances in the T-shape gate E-mode AlGaN/GaN MIS-HEMT. C₂ is the channel capacitance performing in the E mode and C₁/C₃ is the gate-source/drain overlay capacitance performing in the depletion mode (D mode). Multi-frequency C–V measurements were conducted on the T-shape gate E-mode MIS-HEMT with source and drain both grounded (shown in Fig. 3(b)), and the C_G–V_G curves are shown in Fig. 3(c). Two pinch-off points are observed in the whole V_G range, corresponding to different capacitance components. The first one at V_G ~ –10 V is related to the overhang capacitances (i.e., C₁ and C₃), and the second one is related to the E-mode channel (i.e., C₂). Very small frequency dispersion is observed on both E-mode gate and D-mode gate overhang, informing a high quality ALD-SiN_x/(Al)GaN and LPCVD-SiN_x/(Al)GaN interface. Unlike the E-mode portion, the D-mode portion exhibits a noticeable hysteresis between up- and down-sweeping curve, probably caused by deep interface/bulk states in the LPCVD-SiN_x passivation dielectric.

Since the Miller capacitance C_GD plays an important role on the device switching performance, in this paper, C_GD was individually investigated by C–V measurement with a shorted source/gate terminal and a sweeping drain terminal, as shown in Fig. 4(a). In this measurement, drain terminal voltage (V_DG) is swept from an initial voltage V_init (holding for 30 seconds before C–V sweep) to 25 V and double-mode sweep was used to estimate the instability of the C_GD. It is noted that a negative V_DG, corresponding to a positive bias applied on the overhang capacitor, is able to assist the spill-over of the electrons to the SiN_x/(Al)GaN interface as well as the trapping of the interface or dielectric bulk states. Fig. 4(b) plots the measurement results and an obvious hysteresis (> 1.5 V) on the up- and down-sweep D-mode pinch-off voltage is obtained, which is directly dependent on the magnitude of the negative stress voltageV_init. The hysteresis increases owing to the enhanced trapping in the passivation dielectric. In the down-sweep curves under different initial stress, the D-mode pinch-off voltage merges together, indicating that an efficient electrons’ de-trapping is achieved with a 25 V V_DG.

In this work, to further identify the effect of the overhang capacitance on the device switching performance, a double-pulse measurement was executed with measurement setup plotted in Fig. 5(a). A device bare die was mounted on a testing PCB by conductive silver epoxy, and its pads were bonded out by golden wires. A simple gate driver circuit is used with a separate turn-on and turn-off path. In order to enlarge the Miller plateau, a 10 kΩ charging resistor was used to slow down the turning-on process. The waveform of inductive switching under 50 V V_BUS and the turn-on transients are shown in Figs. 5(b) and 5(c). During the turn-on period of the second pulse, the presence of the D-mode portion of C_GD reduces the slew rate of output voltage, leading to a longer Miller plateau and extra switching power loss. The turning point of two sections of dV_DS/dt is around 10 V in the beginning of Miller plateau, which coincides with the pinch-off voltage of C_GD.

In this work, gate-related capacitances of the T-shape-gate E-mode AlGaN/GaN HEMT have been investigated by C–V measurements and the inductive switching measurement. The overhang-related C_GD exhibits a noticeable hysteresis in double sweeps, informing its sensitivity to forward stressing voltage due to the trapping of deep interface/bulk states of LPCVD-SiN_x passivation dielectrics. During the turn-on period of inductive switching measurement, two sections of dV_DS/dt with a turning point around 10 V are observed for the presence of D-mode portion in C_GD, leading to a longer switching transfer and higher switching power loss.

This work was supported in part by the National Natural Science Foundation of China under Grant 61822407, Grant 61527816, Grant 11634002, Grant 61631021, Grant 62074161, Grant 62004213, and Grant U20A20208; in part by the Key Research Program of Frontier Sciences, Chinese Academy of Sciences (CAS) under Grant QYZDB-SSW-JSC012; in part by the Youth Innovation Promotion Association of CAS; in part by the University of CAS; and in part by the Opening Project of Key Laboratory of Microelectronic Devices & Integrated Technology, Institute of Microelectronics, CAS.