Portable electronic devices such as mobile phones and laptops, are almost completely integrated into every aspect of people’s daily life, which puts higher demands on the performance of the power management systems^[1-5]. DC–DC converters are used to generate many different output voltages from battery power supplies based on particular applications. That is the reason why control methods of the switching power supply are the main influencing factors of conversion speed and accuracy^[6]. Feedback control methods of the buck converter are mainly divided into voltage mode and current mode. Current-mode modulation has a faster transient response due to the direct feedback path from the inductor compared with voltage-mode control. Furthermore, a better output voltage with less voltage ripple can be obtained^{[7, 8]}. Currently, switching power supplies are developing towards lower input voltages with a wide input range. Therefore, the valley current control mode is increasingly receiving attention and application.

A common method to increase the power efficiency of buck converter is the constant on-time (COT) pulse frequency modulation (PFM) method^[9-11]. The traditional voltage mode COT control method has always been popular among researchers thanks to its simple circuit configuration, which can be realized just using a simple on-time control module and does not need a compensation network^[12]. However, due to its constant on-time, it can only adapt to changes in input voltage, load current and output voltage by adjusting its switching period. If the switching frequency changes with the working conditions during the normal operation of the converter, it will bring serious electromagnetic interference (EMI) problems to the circuit, which affects the sensitivity of the phase-locked-loop (PLL) circuit and the ratio frequency integrated circuits^[8]. Pulse width modulation (PWM) method can be used under high load current conditions to maintain a constant frequency^[13-15]. But as the load current decreases, the power dissipation on the switches takes up a major part of the overall power consumption if the switching frequency remains at the initial constant value. Therefore, researchers have also proposed some methods of constant frequency modulation^[16-18].

In this paper, an adaptive on time (AOT) valley current mode control scheme is proposed in which the on-time can be adjusted dynamically during CCM and the frequency decreases with the load current under DCM. Constant frequency under CCM can reduce the adverse effects of frequency changes on the output while minimizing the electromagnetic problem simultaneously, which is beneficial to the design of the subsequent filter circuit. For circuit implementation, a simple and accurate zero current circuit is adopted, which allows the converter to switch smoothly between the two conduction modes without the need for an additional mode selection circuit. The rest of the paper is organized as follows. The design of several key modules is presented in Section 2. Simulation results and related analysis are given in Section 3. Finally, the paper is concluded in Section 4.

The system block diagram of the proposed adaptive on-time controlled buck converter is illustrated in Fig. 1 which is composed of power stage and feedback control stage. The power stage primarily includes two power transistors for on-off switching and a LC filter, passing the energy from the input to the output^[19].

The output voltage is divided by resistor R₁ and R₂ to produce a partial voltage V_FB, which is used to compare with a reference voltage V_ref. The current sensing circuit detects the current of the freewheeling transistor, and the detected signal V_SEN is input to the comparator simultaneously with the output of the error amplifier. When V_SEN is lower than V_c, the high level generated by the comparator is fed back to the power stage to turn on the P switch through a series of control modules. At the same time, the N switch is turned off to increase the output voltage until V_FB raises to V_ref. Then, the next conversion cycle starts. A filter network consisting of capacitor C₀ and inductor L produces a steady DC output voltage for DC–DC conversion.

In contrast from the traditional commonly used peak current mode control, this paper uses the valley current mode control and the advantages of the valley current mode are reflected in the following aspects.

(1) A lower duty cycle voltage conversion can be achieved, that is, a large input with a low output. When the duty cycle is reduced, the P switch has a shorter on-time, which put higher requirements on the performance of the conventional current sensing circuit. While the free-wheeling transistor has a longer on-time, so that the current sampling is more convenient.

(2) Better transient response performance. Unlike systems that use peak current mode control, the status of the power transistor which is controlled by the valley current mode is not synchronized with the clock signal, so it can be turned on or off at any time.

To eliminate the adverse effects of the varying frequency, parameters related to the switching frequency under CCM is analyzed theoretically:

${V_{\rm{L}}} = L \times \frac{{{\rm d}{i_{\rm{L}}}}}{{{\rm d}t}} \Rightarrow \Delta {I_{\rm{L}}} = \frac{{{V_{\rm{L}}}}}{L} \times \Delta T.$ (1)

In the conduction phase of the P switch, the change of inductor current is calculated as follows:

$\Delta {I_{\rm{L}}}\left( + \right) = \frac{{\left( {{V_{{\rm{in}}}} - {V_{{\rm{DSP}}}} - {I_{\rm{L}}} {R_{\rm{L}}}} \right){{ - }}{V_{\rm{o}}}}}{L} \times {T_{{\rm{ON}}}}.$ (2)

In the off phase of the P switch, the change of the inductor current is as follows:

$\Delta {I_{\rm{L}}}\left( - \right) = \frac{{{V_{\rm{o}}} + \left( {{V_{{\rm{DSN}}}} + {I_{\rm{L}}} {R_{\rm{L}}}} \right)}}{L} \times {T_{{\rm{OFF}}}}.$ (3)

When the circuit operates under steady state, the increase in inductor current in each cycle is equal to the amount of reduction. Therefore, the switching period can be obtained from Eq. (2) and Eq. (3):

${T_{\rm{s}}} = \frac{{{V_{{\rm{in}}}} - {V_{{\rm{DSP}}}} + 2 {I_{\rm{L}}} {R_{\rm{L}}} + {V_{{\rm{DSN}}}}}}{{{V_{\rm{o}}} + {V_{{\rm{DSN}}}} + {I_{\rm{L}}} {R_{\rm{L}}}}} \times {T_{{\rm{ON}}}},$ (4)

where the quantity, R_L, is the equivalent resistance of the inductor. V_DSP and V_DSN represent the forward voltage drop of the P switch and the N switch, respectively. Since in a well-designed buck converter these parameters are quite small compared to the DC value of V_in and V_o, they can be neglected in the calculation process. The simplified calculation result is as follows:

${T_{\rm{s}}} = \frac{{{V_{{\rm{in}}}}}}{{{V_{\rm{o}}}}} \times {T_{{\rm{ON}}}}.$ (5)

To keep the switching frequency unchanging in CCM, it is necessary to eliminate the influence of V_in and V_o by adjusting T_ON. Based on the traditional COT control, an input voltage feedforward control loop and an output voltage feedback loop are introduced. So that T_ON would vary with changes of input voltage and output voltage. Thereby, the frequency is stabilized at a constant value. The corresponding on-time is as follows:

${T_{{\rm{ON}}}} = \frac{{k{V_{{\rm{ref}}}}{C_{\rm{1}}}}}{{g{V_{{\rm{in}}}}}},$ (6)

where gV_in represents the value of the voltage controlled current source (VCCS), while kV_ref represents the value of the voltage controlled voltage source (VCVS). It is implemented by the circuit diagram shown in Fig. 2.

Since the actual output voltage is a variable with ripple component, if the output voltage is directly used to control the VCVS, the circuit would have stability problems. A reasonable solution is to use the reference voltage V_ref instead of the output voltage. When the VCCS (gV_in) charges the capacitor C₁ to the voltage of the VCVS (kV_ref), the input terminal of the RS flip-flop, R, will be triggered to high level, which turns the P switch off and turns the N switch on. Upon substituting Eq. (6) into Eq. (5), the final expression of T_S can be obtained as follows:

${T_{\rm{S}}} = \frac{{k{V_{{\rm{ref}}}}{C_{\rm{1}}}}}{{g{V_{\rm{o}}}}} \approx \frac{{k{C_{\rm{1}}}}}{{gm}},$ (7)

where V_O ≈ mV_ref, and the frequency here is constant without the influence of the input and the output voltage.

To analyze the stability of the loop, it is necessary to understand the transfer function of the closed-loop and analyze the impact of the zeros and poles on the system. We then determine whether the compensation network is prerequisite. Ref. [20] gives the categorical modeling method of the open loop for current mode control. In the modeling process, the switches, the inductor, the comparator, and the on-time controller are treated as a single entity, respectively. The describing function method is used to describe the transfer function from the signal V_c to the output signal V_o. The approximate loop gain function of the circuit is given as follows:

$\frac{{{V_{\rm{o}}}}}{{{V_{\rm{c}}}}} = \frac{1}{{{R_{\rm{i}}}}}\times\frac{1}{{1 + \dfrac{s}{{{Q_1}{\omega _1}}} + \dfrac{{{s^2}}}{{\omega _1^2}}}}\times\dfrac{{{R_{\rm{o}}}({R_{\rm{c}}}{C_{\rm{o}}}s + 1)}}{{{R_{\rm{o}}}{C_{\rm{o}}}s + 1}},$ (8)

where Q₁ = 2/π, ω₁ = π/T_ON. It can be seen markly from the transfer function that there are two poles which would cause the instability of the circuit.

To deal with this problem, a compensation network is indispensable for the system design. In this paper, a type Ⅱ compensation network is introduced at the output of the operational amplifier, which is composed of parallel connection of resistor R_c, capacitor C_c and C_p, as shown in Fig. 1. This compensation network introduces two poles, while R_c and C_c are connected in series to produce a left half plane zero. This zero would compensate one pole of the original circuit by adjusting the magnitude of resistor R_c and capacitors C_c, C_p suitably. The gain point is extrapolated to make the feedback system more stable.

The loop-compensated transfer function is simulated in MATLAB and the Bode plot is shown in Fig. 3. The simulation is performed under the conditions of input and output voltage are 5 V and 1.8 V respectively, with the load current of 1 A. It can be seen from the Bode plot that the phase margin of the loop is 57.8 degrees, which satisfies the conditions for stable operation of the system.

The buck converter discussed in this paper has a reference voltage of 1 V^[21] and operates at DCM under light load. In other words, when the inductor current drops to zero, the P switch and the N switch are turned off simultaneously to prevent the current from flowing back. In actual situations, when the inductor current drops to zero and the N switch is not turned off in time, there will be a current backflow, which will inevitably result in waste of energy. A zero current detection (ZCD) unit shown in Fig. 4 is added into the dead-time controller to monitor the inductor current. Since the high precision current detection circuit is complicated to design, the voltage V_a is detected actually. When the inductor current decreases, V_a is expressed as:

${V_{\rm{a}}} = - {I_{\rm{L}}} {R_{{\rm{ONN}}}}.$ (9)

In the discontinuous conduction mode, when the inductor current drops to zero, V_a equals to zero, too. Ideally, the moment when V_a is equal to zero is taken as the effective time of the ZCD output signal. However, due to the delay time of different circuit modules inside the converter, when V_a is equal to zero, it will take a delay time for ZCD to turn off the N switch.

As a result, the inductor current is still reversed during this delay time. Therefore, the value of V_a slightly below zero is used as the turning point^[22]. The critical V_a value used in this article is about –2.5 mV. Since the inductor current is always above zero in CCM, the ZCD signal keeps at low level to ensure the zero current detection module works only in DCM.

The overall circuit diagram of the threshold voltage comparator is shown in Fig. 5. In practical applications, resistors R₃–R₆ will be replaced by MOS transistors with constant bias. One of the advantages of this ZCD module, shown in Fig. 4, is that during the half cycle in which the P switch is turned on, that is, during the period in which the inductor current rises, the potential at point X is pulled to zero. As a result, a high level enable signal EN is generated, forcing the output of the threshold voltage comparator to a high level. Consequently, the output of the ZCD module is low during the entire charging process, which avoid a large part of energy loss. When P is high, capacitor C₂ is charged by the current source. While the potential of X rises to a certain threshold, the EN is turned to a low level, allowing the comparator to operate normally.

From this analysis, the switching frequency should be ideally constant regardless of input voltage, output voltage and load current under CCM. The switching period T_s and on-time T_on of the converter is obtained by the simulation with standard 0.18 μm process, which is shown in Fig. 6. It is obvious from Fig. 6(a) that the switching period can be maintained at a quasi-fixed value over a large load range and the maximum changing rate can be controlled within 4%. Furthermore, the duty cycle is almost changeless as the load current if the input and output voltage are constant.

With a constant switching period, because the charge and energy delivered to the output capacitor of each cycle increase as V_in^[11], the required on-time of P switch is reduced as the input voltage increases, as shown in Fig. 6(b). From the simulation results, the maximum changing rate of the switching frequency is about 5% within the test range 2.5–5 V. Conversely, in the case where the input voltage is constant, a larger turn-on time is required to charge the capacitor to obtain a larger output voltage. In other words, the duty cycle increases as the output voltage, as shown in Fig. 6(c). The maximum rate of change of the switching frequency obtained by simulation is approximately 2% within the output voltage range of 0.6–1.8 V. The above simulation results show that the major operation of AOT control is the variation of the duty ratio to obtain an expected frequency of regulator.

Compared with the traditional COT structure, the AOT structure proposed in this paper has better frequency characteristics when the input voltage and output voltage change. Simulation results for the two structures are given in Fig. 7. The output voltage remains constant at 0.6 V when the input voltage changes from 0.8–5.0 V while the input voltage is kept at 5.0 V when the output voltage changes from 0.6–1.8 V. The switching frequency shows to be almost independent on the input voltage and output voltage under AOT control while the switching frequency of COT control varies dramatically with V_in and V_o. As we all know that a constant frequency is more conductive to the design of subsequent filter circuits and contributive to the stability of the whole system.

The ability for a converter to return to its steady state after the load current changes illustrates the robustness of the circuit^[23–25]. Fig. 8 shows the load transient waveforms. The output recovers its desired level with the error smaller than 1% in 6 and 2 μs, respectively, for the step-up and step-down load current steps between 0.4 and 1.2 A. In addition, the overshoot and undershoot voltages can also be controlled within 14 mV.

The output voltage ripple is composed of capacitor ripple and ESR ripple. So, the total ripple can be expressed as follows:

$\begin{array}{l} \Delta {V_\rm{o}} = \Delta {V_\rm{c}} + \Delta {V_{\rm{ESR}}} = \Delta {i_\rm{L}}\left({R_{\rm{ESR}}} + \dfrac{1}{{8{f_\rm{s}}{C_\rm{o}}}}\right) \\ \,\quad\quad =\dfrac{{{V_\rm{o}}({V_{{\rm{in}}}} - {V_\rm{o}})}}{{{f_\rm{s}}L{V_{{\rm{in}}}}}}\left({R_{\rm{ESR}}} + \dfrac{1}{{8{f_\rm{s}}{C_\rm{o}}}}\right).\end{array}$ (10)

In CCM, the switching frequency is quasi-constant, so that the amplitude of the output ripple is fixed at a constant value for a given input voltage and output voltage. It can also be seen from Fig. 8 that the magnitude of the output ripple is constant when only the load current changes. This phenomenon has been theoretically verified in Ref. [26].

To better illustrate the transient response characteristics of the AOT structure, comparisons in Table 1 are made to the two structures mentioned in Ref. [24] in voltage drop, voltage overshoot and recovery time. The standard of normalization is the characteristics of PWM structure. Its voltage drop is about 45 mV while the overshoot voltage is about 75 mV with a recovery time of 200 μs. From Table 1, the AOT control has faster transient performance and smaller voltage variation than PWM and COT control under load current steps.

Load regulation rate is one of the ways to measure the performance of a power supply, which would reflect changes in output voltage as a function of load current. Its expression is as follows:

$\eta = \frac{{{V_{\rm{o1}}} - {V_{\rm{o2}}}}}{{{V_{\rm{ref}}}\left( {{I_{\rm{o1}}} - {I_{\rm{o2}}}} \right)}}.$ (11)

Actually, a change in the output load of the power supply will cause a slight change in the output voltage. For a good power supply, the changes of the output voltage due to load changes are small, typically 3%–5%. In this paper, the load regulation rate is measured under the condition of 1.2 V output voltage with the load current switching from 0.1 to 1 A. The simulation diagram is shown in Fig. 9 and the result is 0.19% after calculation, which is within acceptable limits.

The line regulation of the converter with AOT mode is also obtained as expected. The ripple voltage is higher with a lower load current because the ripple voltage is inversely proportional to the switching frequency.

The power efficiency is simulated versus the load current and the output voltage as shown in Fig. 10. The peak power efficiency is 95.5% when the load current is 0.95 A and the output voltage is 1.8 V. As can be seen from the figures, the overall trend of the conversion efficiency increases first and then decreases. The load currents corresponding to the broken lines in Fig. 10 indicate that the critical current is related to different output voltages. The crossover losses between the two switches are the main factors of the efficiency losses under light load current conditions which is because the moment when the P switch is turned off, the current flowing through it cannot fall to zero immediately and there is a voltage drop across the P switch, resulting in extra power loss in the case where current and voltage both exist. Meanwhile, there are similar power loss on the N switch.

When the load current is reduced to make the converter enter DCM, the conversion efficiency can still maintain a high level over a large load range, especially when the output voltage is higher than 1.8 V. Until the current drops below about 0.1 A, the conversion efficiency drops significantly. The smaller the output voltage, the more obvious the trend. Under extremely light load conditions, the efficiency is greatly reduced due to the increasing proportion of quiescent current. To offset the switching loss, lower switching frequencies are adopted in DCM.

The maximum conversion efficiency under different control methods are further compared in Table 2. The maximum conversion efficiency of AOT can reach 95.5% when the output voltage is 1.8 V. As the output voltage decreasing, the conversion efficiency decreases slightly. The maximum conversion efficiency is about 92% with 0.6 V output voltage. The light load efficiency of the traditional PWM control mode can only reach about 20% while the efficiency of this AOT structure can reach 40% or more. Consequently, the conversion efficiency, especially the conversion efficiency under light load is improved. The performance summary of this design is presented in Table 3.

An adaptive-on-time valley current mode controlled buck converter with characteristics of constant frequency in CCM and variable frequencies in DCM is proposed for the application of wide current range and high power efficiency. The proposed converter is designed in standard 0.18 μm process, and composed of power and feedback control stages. First, this circuit can not only solve the problem caused by changing frequency of the traditional COT method but can also improve the conversion efficiency under light load compared with the PWM control mode. Second, it can operate stably under different conduction modes and transform freely without introducing large undershoot voltage and response time. The increase in the allowable output range and effective control of the voltage undershoot make the design of subsequent circuits less difficult. In addition, due to the introduction of variable frequency control in DCM, the overall switching efficiency is greatly improved. Simulation results show that the peak conversion efficiency can reach 95% with 1.8 V output in a large load current range. Besides, the efficiency can be improved as the voltage rises within a certain range, which is more suitable for battery supplied systems.

This work was supported by the National Natural Science Foundation of China (No. 61974116).