Fully differential (FD)^[1–4] circuits have become the most widely-used configurations in the design of electronic circuits and systems because they provide better elimination of clock feed through, charge rejection errors and power supply noises when compared to its single-ended counterparts^[5]. The second-generation current conveyor (CCII) is a highly versatile single ended current-mode building block; however, high-performance analog integrated circuits today incorporate fully differential signal paths. In 2005, El-Adway et al. introduced a fully-differential current conveyor (FDCCII), which possess a larger output dynamic range, higher design flexibility, wide bandwidth, high slew rate, low power consumption and reduced harmonic distortion when compared to CCII. Consequently, analog designers were significantly boosted to realize FDCCII based circuits. Despite the known merits, comparatively little work has been accomplished using FDCCII as far back as 2005. The main reasons for refraining from their utilization are discussed in the following.

The FDCCII structures that were reported in the literature employed large supply voltages, as high as 5 V^[6]. However, in 2014, Kumngern et al. introduced a low voltage structure^[7] using the bulk driven technique^[8]. The operating supply was reduced to 0.5 V. While the semiconductor industry races toward lower-technology nodes still in FDCC structures transistor technology, ranging from 0.35 μm to as large as 1.2 μm^{[5–6, 9]}. This was scaled down to 0.18 μm as reported in Ref. [7], but this challenge remains. Since the FDCCII block comes with the inherent advantage of realizing multifunctional filters using a single block^{[4, 6, 10]}, this leads to an issue in the non-independent tuning of ω_o and Q. In these cases, the same parameter or code-word affects the Q factor, ω_o and sometimes gain concurrently. The reconfigurable feature of an analog cell is a prominent characteristic in several applications. Most of the existing FD circuits^[11–13] utilize either op-amps, DXCCII, DVCCII, DDCC or some other variant. If a FDCCII block has been used to design an application, then only analog tuning has been discussed. Digital control of FDCCII block has not been explored, which leaves open the possibility to realize more digitally controlled FDCCII-based ASP applications.

The motivation of this treatise is to present the facility of independent analog and digital tuning of FDCCII-based analog signal processing applications related to theser two concerns. The rest of this paper is structured as follows. The first section presents a fully differential second order low-pass/band-pass filter using a six terminal CMOS FDCCII. The FDCCII is then reconfigured through digital programmability by introducing a current division circuit. Finally, a new digitally controlled FDCCII integrator and differentiator are also presented in the last section.

FDCCII (see the block diagram of Fig. 1(b)) has two differential X, Y and Z terminals. The fully differential buffer forces V_Xd to follow V_Yd. The FDCCII structure (see Fig. 2) has only 23 transistors unlike the available fully differential structures with 39 transistors in Refs. [9, 14]. The FD buffer consists of two matched differential pair (M₁₀, M₁₃) & (M ₁₄, M₁₇); matched biasing current source transistors (M₁₅, M₁₆) & (M ₁₁, M₁₂); and class AB output stage (M₆–M₉) & (M ₁₈–M₂₁). (M₁–M₃) forms the biasing of output stage and the input is applied at high impedance terminals of NMOS (M₁₃, M₁₄). The DC voltage characteristics of the differential X terminal and the transfer characteristics of the differential Z terminal of FDCCII are depicted by Figs. 3(a) and 3(b) respectively. Voltage and current following actions of FDCCII, as shown by the terminal equations of Fig. 1(a), exhibit nearly rail-to-rail transfer between input and output terminals. The DC current range extends from −100 to 100 mA and the DC voltage range is −1 to 1 V. The characteristic values for the FD-CCII are given in Table 1. Transistor aspect ratios are shown in Table 2.

The Sallen-Key filter,which is particularly valued for its simplicity, is a very popular active filter. It can be used to create 2nd order filter stages that can be cascaded together to form larger order filters. A Sallen-Key LP configuration has been presented in Ref. [15]^① using an op-amp^① and DDA^① in Ref. [16]^①. The authors in Ref. [9]^① have implemented Sallen Key BP response using FBDDA^①. Realization of another Sallen Key BP filter using DDCCII^① is proposed in Ref. [17]^①. Sallen Key filter (LP, BP) response using (AD844) plus type CCII^① is presented in Ref. [13]^①. However, these realizations are either non-CC based or non-fully differential. In our architecture^①, we have realized a voltage mode second order filter using a six terminal CMOS Fully Differential CC, FDCCII^①. The proposed realisation is shown in Fig. 4. V_o1 and V_o2 are low-pass and band-pass responses respectively. Routine analysis yields following output functions:

$ \begin{split} &\frac{{{V_0}_2}}{{V_{\rm in}}} = - \frac{{\mathop {}\nolimits_{\displaystyle\frac{{{G_1}s}}{{{C_1}}}} }}{{{s^2} + s\left( {\displaystyle\frac{{{G_2}_{}}}{{{C_1}}}} \right) + \displaystyle\frac{{{G_4}{G_3}}}{{{C_1}{C_2}}}}},\\ &\displaystyle\frac{{{V_0}_1}}{{V_{\rm in}}} = - \displaystyle\frac{{{G_1}{G_3}/{C_1}{C_2}}}{{{s^2} + s\left( {\displaystyle\frac{{{G_2}}}{{{C_1}}}} \right) + \displaystyle\frac{{{G_4}{G_3}}}{{{C_1}{C_2}}}}},\\ &\omega_{\rm o} = \sqrt {{{{G_4}{G_3}} / {{C_1}{C_2}}}} ,\\ &{{\omega_{\rm o}} / Q} = \displaystyle\frac{{{G_2}}} {C_1},\\ &Q = \displaystyle\frac{1}{{{G_2}}}\sqrt {{{{C_1}{G_4}{G_3}} / {{C_2}}}} . \end{split} $  ()

As evident from these equations, analog tuning of the gain can be achieved by using G₁, ω_o by setting C₁/C₂ and Q by using G₂. The filter gain can be expressed as: H_LP = −G₁/G₄, H_BP = −G₁G₂.

The voltage gain between differential X and Y terminals, here, is not crucial because unity negative feedback has been employed in the realization. Considering the deviation of current gain involving differential X and Z terminals and taking the non-ideality into account, namely, I_zdi = α_iI _xdi, where i = 1, 2, 3, α = 1–ε and ε (|ε| 1) is the FDCCII current tracking error, the output LP and BP functions of the proposed filter can be expressed as:

$ \begin{aligned} &\displaystyle\frac{{{V_0}_2}}{{V_{\rm in}}} = - \displaystyle\frac{{\mathop {{}}\nolimits_{\displaystyle\frac{\alpha _1{{G_1}s}}{{{C_1}}}} }}{{{s^2} + s\left( {\displaystyle\frac{{{G_2}_{}}}{{{C_1}}}} \right) + \displaystyle\frac{{{\alpha _3}{\alpha _2}{G_4}{G_3}}}{{{C_1}{C_2}}}}},\\ &\displaystyle\frac{{{V_0}_1}}{{V_{\rm in}}} = - \displaystyle\frac{{{\alpha _1}{\alpha _2}{G_1}{G_3}/{C_1}{C_2}}}{{{s^2} + s\left( {\displaystyle\frac{{{G_2}}}{{{C_1}}}} \right) + \displaystyle\frac{{{\alpha _3}{\alpha _2}{G_4}{G_3}}}{{{C_1}{C_2}}}}},\\ &\omega_{\rm o} = \sqrt {{{\alpha _3}{\alpha _2}{G_4}{G_3}} /{{C_1}{C_2}}} ,\\ &{{\omega_{\rm o}} / Q} = \displaystyle\frac{{{G_2}}}{C_1},\\ &Q = \displaystyle\frac{1}{{{G_2}}}\sqrt {{{{\alpha _3}{\alpha _2}{C_1}{G_4}{G_3}} / {{C_2}}}} . \end{aligned} $  ()

The sensitivities of different filter specifications are summarized below.

$ \begin{aligned} &{S^{\omega_{\rm o}}}_{\alpha_2,\alpha_3,G_4,G_3} = - {S^{\omega_{\rm o}}}_{C_2,C_1} = \frac{1}{2},\\ &{S^{\omega o}}_{\alpha_2,\alpha_3,G_4,G_3,C_1} = - {S^Q}C_1 = \frac{1}{2},\\ &{S^Q}G_2 = - 1. \end{aligned} $  ()

The proposed circuit enjoys attractive sensitivity measure. All active and passive sensitivity figures are within reasonable limits. The filter has been realized using three FDCCII blocks, using only four resistors and two capacitors. This component count is less than most of the available Sallen-Key realizations and offers the same number of output functions. It can also independently tune Q and orthogonal control of ω_o & Q.

SPICE simulations were carried out to verify the potential of proposed second-order filter. When R₁ takes values from 1.3 to 0.4 kΩ decreasing with a step size of 0.3 kΩ, gain of the LP & BP filter is found to be increasing. As R₁ decreases, value of G₁ increases because the two are reciprocal of each other. R₁ takes values equal to {1.3, 1, 0.7, and 0.4 kΩ} for plotting low-pass and band-pass response with variable gain, as given in Figs. 5 and 6. f_o has been fixed at 13 Hz and Q = 1.02 for LPF & Q = 4.08 for BPF. This variation of filter gain with resistor R₁ is in agreement with the transfer functions, V₀₁ and V₀₂, as calculated at the beginning of Section 3. Tuning of Q-factor has been achieved by varying R₂ as {8, 12, and 16 kΩ}. Here, the BP filter’s gain (see Fig. 7) can be seen to vary with R₂, which again verifies the theoretical calculations. Pole-ωo tuning can be achieved by programming C₁, C₂ using capacitor array^{[9, 14]}. However, the capacitor array requires more chip area but they reserve high linearity of the filter and also allow direct interfacing with digital signal processing section of receiver^[9]. The circuit employs floating capacitors which are now standard and implemented with advanced IC design techniques. These new IC technologies realize floating capacitors as a double poly (poly1-poly2) capacitor^[18]. A basic and a comparative detail of the performance of proposed realization have been summarized in Tables 3 and 4 respectively.

Current transfer characteristics of FD-CCII block with digital control is shown in Fig. 9. Both the integrators and differentiators are prominent blocks that find applications in analog-to-digital convertors (ADCs), wave shaping circuits and continuous-time filter structures. They are considered to be very important units in the design of analog integrated and mixed-signal circuits. The output signal in an integrator is nothing but the time integral of the incoming signal. As for the differentiator, its output is directly proportional to the rate of change of the input. Earlier, most of the RC integrator and differentiator circuits were designed using operational amplifier. The major drawback of using these op-amp based circuits is that they don’t provide a spacious bandwidth and wider dynamic range. Subsequently, a few circuits have been proposed employing different current voltage-mode devices, such as OTA, CC, CCTA, etc. In this paper digitally programmable VM integrator and differentiator are shown in Fig. 10. These circuits consist of a single DCFDCCII, capacitor and resistor. They not only have the advantages of being differential but they also have versatile programmability. A routine analysis of the circuits yields the following outputs:

Fig. 8(a) shows a 6-bit M-2M ladder classical circuit which is employed at Z+ and Z- terminals of FDCCCII. Current division circuit divides input current into two branches depending on the value of a set of programmed bits. In our case, I_out1 is the ladder output that depends on the value of the α and I_out2 is grounded. N is the digital codeword. The input current is multiplied by a factor alpha, which depends on value of the first 6-bits according to:

$\begin{split} &{I_{{\rm{out}}1}} = {{a}}{I_{{\rm{in}}}} \wedge {{a}} = \frac{1}{{{2^n}}}\left( {\sum\limits_{j = 0}^{n - 1} {{b_j}{2^j}} } \right)\;{\rm{with}}\;{{n}} = 6\;\\ &\quad {\rm{where}}\;{{N}} = \sum\limits_{j = 0}^{n - 1} {{b_j}{2^j}} . \end{split}$  ()

$ \begin{split} &V_{\rm out} = \frac{{\alpha V_{\rm in}}}{{sCR}},\\ &V_{\rm out} = \alpha sCRV_{\rm in}. \end{split} $  ()

As evident from these equations, the time constant of the integrator and differentiator are programmable through digital code word alpha. The digital control module (CDC) is implemented for 6-bit. The circuits are simulated with SPICE tool of the TSMC 0.25 μm CMOS process. A pulse input of −0.5 to + 0.5 V and 10 μs time period is applied (high for 5 μs and low for 5 μs). The VM integrator circuit is designed for R = 2.5 kΩ, C = 400 pF. The observed wave shapes for different control word alpha are shown in Fig. 11. The VM differentiator circuit is designed for R = 500 kΩ and C = 13 nF. An input with magnitude 0.5 V is applied and wave shapes observed for different control word alpha are shown in Fig. 12.

The input and output noise spectral densities for CMOS FDCCII based reconfigurable integrator and differentiator are presented in Figs. 13(a) and 13(b). This verifies the essential input to output noise-suppression capability of a differential building block. All of the results that we obtained confirm the theory. The performance of the two realizations is summarized in Table 5.

A second order LP/BP filter and reconfigurable integrator and differentiator have been realized using CMOS based FDCCII and its digital variant DCFDCCII respectively. The filter has independent analog tuning of gain, ω_o and Q. The integrator's and differentiator's response are digitally controlled. Our simulation results are based on 0.25 μm technology and 1.5 V supply voltage. This is our dedicated effort to present the facility of analog and digital tuning of FDCCII block.

The authors would like to thank Department of Electronics, Jamia Millia Islamia University and UGC for providing valuable support in form of the NET-JRF grant.