There has recently been considerable interest in monoclinic β-phase of gallium oxide (β-Ga₂O₃) inspired by its excellent material characteristics—large energy bandgap E_G ~ 4.9 eV^[1], high breakdown electric field E_Br up to 8 MV/cm^[2], and high electron velocity v_sat ~ 1.5 × 10⁷ cm/s^[3]. Wide variety of intentional n-type dopants—Si, Ge, and Sn as shallow donors facilitate to achieve electron concentrations ~ 1 × 10²⁰ cm^–3[4], although p-type doping in Ga₂O₃ shows inconsistent findings^{[5, 6]}. Additionally, with the help of low-cost melt growth techniques, such as Czochralski^[7], and floating zone^[8], large size Ga₂O₃ bulk substrate can be grown and thus offers cost competitiveness over other wideband semiconductors—GaN and SiC. The availability of low cost and large size β-Ga₂O₃ bulk crystalline substrates further enables different epitaxial technologies, such as molecular beam epitaxy (MBE), and halide vapor phase epitaxy (HVPE) to grow Ga₂O₃ with low crystal defects on native substrate. To compensate unintentional Silicon (Si) incorporation during growth of Ga₂O₃, deep level acceptors such as Mg, and Fe are used to achieve semi insulating bulk crystals^[2], and controls substrate leakage. Out of the promising n-type dopants, Si, Ge, and Sn; Ge shows preferred choice for β-Ga₂O₃ devices^[4].

Several experimental studies on defects throughout the entire bandgap of β-Ga₂O₃ (010) layers have used deep level transient spectroscopy (DLTS) and deep level optical spectroscopy (DLOS) techniques^[9–12]. Three distinct trap states at w_C – 0.1 eV, 0.2 eV, and 0.98 eV in Ge-doped (010) β-Ga₂O₃ grown using plasma assisted MBE^[9], E_C – 0.62 eV, 0.82 eV, 1 eV in unintentionally doped (UID) (010) β-Ga₂O₃ using edge-defined film-fed growth (EFG)^[10], E_C – 0.55 eV, 0.74 eV, and 1.04 eV^[11] in β-Ga₂O₃ crystal grown using Czochralski method, and two deep level traps at E_C – 0.78 eV (due to Fe impurities) and E_C – 0.75 eV (due to intrinsic defect)^[12] in upper part of the bandgap with concentrations varying from 10¹⁴ to 10¹⁶ cm⁻³ have been demonstrated.

With the distinct trap level defects reported so far, device performance can be easily questioned unless different trap sources and their individual effects on specific output parameters are fully established because device degradation may be reversible or permanent in nature. Significant progress in Ga₂O₃ based electronic devices such as Schottky diodes^[13], metal semiconductor FET (MESFET)^[2], metal oxide semiconductor FET (MOSFET)^{[14, 15]}, modulation doped FET (MODFET)^[16], and HEMT^[17] have been reported with good DC and RF performance, mainly due to Ga₂O₃ excellent material properties. Traps in the device can affect thermal characteristics, including on resistance (R_on) and threshold voltage (V_Th), a shift of 0.78 V in V_Th was measured due to two distinct trap levels at 0.7 eV, and 0.77 eV in β-Ga₂O₃ MESFETs on Fe-doped β-Ga₂O₃ substrate^[18]. Dynamic dispersion in drain characteristics led current lag due to trap at E_C − 0.75 eV was demonstrated in back-gated Ga₂O₃ based MOSFET^[19].

Potential application of β-Ga₂O₃ based devices beg the question of whether the device degradation due to various traps E_C – 0.98, 0.82, 0.78, 0.75 eV^{[9, 10, 12]} is temporary or permanent in nature? In this work, we focus on traps originated from Fe-doped β-Ga₂O₃ substrate, and Ge-doped epitaxial layer on Sn-doped β-Ga₂O₃ substrate to model the reversible current collapse phenomenon along with measurement of current recovery time to its steady state value.

Fig. 1 shows device structure of AlN/β-Ga₂O₃ HEMT which is analysed in this report. The sequence of materials comprise of 25 nm AlN barrier layer on 2 μm β-Ga₂O₃ substrate. Gate material of Au/Ni with gate length, L_G of 0.25 μm and Schottky barrier height of 0.8 eV is set by fixing the work function, ϕ_M of the gate metal of 2.2 eV, electron affinity of the AlN barrier is set as 1.4 eV^[20] in material properties. Source/drain electrodes are considered to be perfectly Ohmic. The gate–source (L_GS), gate–drain (L_GD), and source–drain (L_SD) spacing are 1.2, 2.95, and 4.4 μm, respectively. Silicon nitride (Si₃N₄) insulator of 25 nm is used as surface passivation to suppress current collapse as per experimental device^[2].

Using electron and hole effective masses of β-Ga₂O₃^[21], total conduction band (N_C) and valence band (N_V) density of states of 3.6 × 10¹⁸ and 2.86 × 10²⁰ cm⁻³, respectively, were calculated, and other parameters were considered from Ref. [17].

For undoped AlN layer default material parameters as mentioned in Ref. [22] are considered except electron affinity (χ = 1.4 eV). Due to low in-plane lattice mismatch between AlN/β-Ga₂O₃ heterojunction, spontaneous and piezoelectric polarization built in model^[22] is activated for AlN material region. A large conduction band offset (CBO), ΔE_C = 1.75 eV^[20] offers polarization induced sheet charge density σ = 5.617 × 10¹³ C/cm^2[23] at the heterointerface due to sole polarization of AlN layer. In absence of p-type carriers, β-Ga₂O₃ based devices are unipolar, so negative differential mobility model as given by Eq. (1) is chosen for β-Ga₂O₃ material region and default values of parameters^[22] are replaced by mobility model^[3]. The low-field electron mobility of 140 cm²/(V·s) as reported in Ref. [3] is in good agreement with Hall measurements electron mobility of 162 cm²/(V·s)^[17].

${\mu _{\rm{n}}}\left( E \right) = {\rm{}}\dfrac{{{\mu _{{\rm{n}}0}} + {\rm{}}\dfrac{{v_{\rm{sa}{{\rm{t}}_{\rm{n}}}}}}{E}{\rm{}}{{\left( {\dfrac{E}{{{\rm{ECRITN}}}}} \right)}^{{\rm{gamman}}}}}}{{1 + {\rm{}}{{\left( {\dfrac{E}{{{\rm{ECRITN}}}}} \right)}^{{\rm{gamman}}}}}}.$ ()

Based on previous published reports^[9–12], among the four electron trap levels—E₁, E₂, E₃, and E₄; the most prominent is E₂ and especially dominant in ( 01) sample, and the source of this trap level is intentional dopant Fe^[12]. So to quantify the effect of Fe dopants led current collapse of drain current, the β-Ga₂O₃ substrate is doped with iron (Fe) as acceptor traps with energy level E_C –0.78 eV, and 0.75 eV^[12]. The Fe doping in the substrate has a Gaussian profile with peak concentration of 10¹⁸ cm^–3 at y = 1.0 μm, and gradually drops to 10¹⁶ cm^–3 near the surface. In order to analyse the effect of traps, generated by commonly used n-type dopants, Ge in β-Ga₂O₃ epitaxial layer, three trap levels at E_C −0.1 eV, −0.2 eV, −0.98 eV are uniformly doped in 50 nm buffer layer. In this case, the substrate is doped with n-type dopant (Sn) concentration of 10¹⁸ cm^–3 to minimize the Fe effect in epitaxial layer as demonstrated in Ref. [9]. The state E_C –0.98 eV is also confirmed by Zhang etal.^[10] as E_C –1.0 eV by DLTS in Ni/β-Ga₂O₃ Schottky diode on unintentional doped (UID) (010) substrate by edge-defined film-fed growth (EFG). All the trap levels are analysed in regard of current collapse phenomenon and are summarized in Table 1 with other characteristics. Only deep level traps with concentration ≥ 10¹⁵ cm^–3 are considered.

The proposed device is analysed under three different conditions—gate stress, drain stress, and gate–drain stress. In all three bias conditions, device is biased in low stress and high stress state for 0.1 to 1 ms with respective DC bias at the gate and drain terminals. During initial bias condition, the device is simulated for output drain current under DC bias at gate and drain terminal. After applying a DC bias of V_GS = 0 V and V_DS = 5 V, this initial bias condition is maintained for 1 ms in dynamic mode. Then, the device is pulsed into high stress state, −25 V on the gate (in gate stress condition); 25 V on the drain terminal (in drain stress); and −25 to 25 V on the gate and drain terminals respectively for another 1 ms, as shown in Fig. 2. Then, the device is returned to its original bias condition. Since we are analysing the recoverable current collapse phenomenon which is not permanent in nature^[24], in post-stress condition traps should gradually return to steady state occupancy state. To quantify the recovery time to steady state, bias condition is analysed for a longer time in the order of 10⁵ s in post stress condition. Fig. 3 shows current collapse phenomenon resulting of stress bias, as shown in Fig. 2. The drain current spikes momentarily to its maximum value corresponding to V_GS = 0 V and V_DS = 25 V and collapses at 2 ms. The trapping of electrons in deep level defects causes this undesirable effect and degrades the device performance.

To analyse the effect of these deep level traps under gate-stress condition, the drain bias remains at fixed bias of 5 V; the device is driven into pinch-off (high stress at gate –25 V for 1 ms) followed by steady state bias. The resulting drain current collapse and recovery time is shown in Fig. 4. It is evident that current degrades momentarily and almost full current recovery happens at time t = 2 ms.

Similar steps are performed to simulate the device under drain stress with appropriate drain and gate bias and the results are shown in Fig. 5. Due to the low concentration (10¹⁴ cm⁻³) of deep level traps at E_C − 0.1 eV, − 0.2 eV in Ge-doped epitaxial layer there is no current collapse phenomenon observed. In gate and drain stress bias conditions, both terminals are put in high stress for 1 ms with − 25 V at gate and 25 V at drain terminal. The results are shown in Fig. 6. Current collapse is evident mainly due to traps at E_C –0.82 eV with recovery time of almost 10 min. The trap level at E_C – 0.98 eV demonstrated in Ge-doped epitaxial layer contributes negligibly in current collapse, but steady state drain current restores after a time elapse of 1 h. The other two trap levels E_C – 0.75 eV, 0.78 eV show significant current collapse and recovery time of few seconds to few minutes are quantified respectively, the later one having large capture cross section of 10⁻¹⁴ cm⁻².

The ionized Fe trap occupancy before and after high stress bias condition highlights are shown in Fig. 7. It can be seen that the trap density under the gate and gate source area near the surface mostly affects the current degradation. Ionization trap density is plotted at a depth of 0.5 μm from the surface in the β-Ga₂O₃ substrate. There is a significant difference in the occupancy of trap along the depth in the substrate and along the horizontal direction towards gate. The gate length of the analysed device, L_G of 0.25 μm, and the effect of Fe trap occupancy extends along the depth up to 0.5 μm (two times of gate length), and along source and drain regions. Source, gate, and drain electrodes are shown in upper part of Fig. 7 to correlate device dimension with ionized trap density in the substrate.

The trapping effects led current collapse phenomenon using drain transient characteristics of β-Ga₂O₃ HEMT is presented. The recovery time for the drain current to return to its steady state value is investigated using Atlas TCAD simulations. The trap level at energy E_C – 0.8 eV in Fe-doped β-Ga₂O₃ substrate plays crucial role in undesirable current collapse phenomenon and the recovery time is about 10 min. In the Ge-doped β-Ga₂O₃ epitaxial layer, the trap level at E_C – 0.98 eV insignificantly degrades the drain current but takes roughly 1 h to restore the original value. This current degradation is reversible event and current returns to its steady state value but only after a finite time varying from few seconds to several minutes depending on the trap characteristics. It is also observed that unintentional interface traps have a negligible effect on current collapse. The report thoroughly establishes that intentional Fe-doping in semi insulating β-Ga₂O₃ substrate led traps cause current collapse, and on the other side recovery time in current lag in Ge-doped β-Ga₂O₃ epitaxial layer is approximately 1 h. By measuring the current recovery time, this report effectively distinguishes between temporary and permanent device degradation due to current collapse. The findings of this work may be useful in reliability study of β-Ga₂O₃ devices.

This publication is an outcome of the collaborative R&D work undertaken in the project under the Visvesvaraya PhD Scheme of Ministry of Electronics & Information Technology, Govt. of India, being implemented by Digital India Corporation.