[1] W H Zhou, S L Zhang, S Y Guo et al. Designing sub-10-nm metal-oxide-semiconductor field-effect transistors via ballistic transport and disparate effective mass: The case of two-dimensional BiN. Phys Rev Appl, 13, 044066(2020).
[2] W H Zhou, S L Zhang, Y Y Wang. Anisotropic in-plane ballistic transport in monolayer black arsenic-phosphorus FETs. Adv Electron Mater, 6, 1901281(2020).
[3] D Y Jeon, M Mouis, S Barraud et al. Channel width dependent subthreshold operation of tri-gate junctionless transistors. Solid-State Electron, 171, 107860(2020).
[4] J P Colinge, C W Lee, A Afzalian et al. Nanowire transistors without junctions. Nat Nanotechnol, 5, 225(2010).
[5] N Mendiratta, S L Tripathi. A review on performance comparison of advanced MOSFET structures below 45 nm technology node. J Semicond, 41, 061401(2020).
[6] J Lee, Y Kim, S Cho. Design of poly-Si junctionless Fin-channel FET with quantum-mechanical drift-diffusion models for sub-10-nm technology nodes. IEEE Trans Electron Dev, 63, 4610(2016).
[7] R Yan, A Kranti, I Ferain et al. Investigation of high-performance sub-50 nm junctionless nanowire transistors. Microelectron Reliab, 51, 1166(2011).
[8] T Rudenko, A Nazarov, I Ferain et al. Mobility enhancement effect in heavily doped junctionless nanowire silicon-on-insulator metal-oxide-semiconductor field-effect transistors. Appl Phys Lett, 101, 053511(2012).
[9] S Gupta, K Nigam, S Pandey et al. Effect of interface trap charges on performance variation of heterogeneous gate dielectric junctionless-TFET. IEEE Trans Electron Dev, 64, 1(2017).
[10] A N Nazarov, I Ferain, N D Akhavan et al. Random telegraph-signal noise in junctionless transistors. Appl Phys Lett, 98, 092111(2011).
[11] O M Berengue, J Chiquito. Direct evidence of traps controlling the carriers transport in SnO2 nanobelts. J Semicond, 38, 122001(2017).
[12] L H Ma, W H Han, H Wang et al. Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors. Chin Phys B, 024, 589(2015).
[13] G X Hu, S Y Hu, J H Feng et al. Analytical models for channel potential, threshold voltage, and subthreshold swing of junctionless triple-gate FinFETs. Microelectron J, 50, 60(2016).
[14] F Y Liu, H Z Liu, B W Liu et al. An analytical model for nanowire junctionless SOI FinFETs with considering three-dimensional coupling effect. Chin Phys B, 25, 047305(2016).
[15] F Ávila-Herreraa, B C Pazb, A Cerdeira. Charge-based compact analytical model for triple-gate junctionless nanowire transistors. Solid-State Electron, 122, 23(2016).
[16] Y Y Liang, Kyungsoo Jang, S Velumani et al. Effects of interface trap density on the electrical performance of amorphous InSnZnO thin-film transistor. J Semicond, 36, 024007(2015).
[17] F Liu, K L Wang, C Li et al. Study of random telegraph signals in single-walled carbon nanotube field effect transistors. IEEE Trans Nanotechnol, 5, 441(2006).
[18] Y Sun, L N Zhang, Z Ahmed et al. Characterization of interface trap dynamics responsible for hysteresis in organic thin-film transistors. Org Electron, 27, 192(2015).
[19] N V Amarasinghe, Z Elik-Butler, P Vasina et al. Characterization of oxide traps in 0.15 μm2 MOSFETs using random telegraph signals. Microelectron Reliab, 40, 1875(2000).
[20] Z Celik-Butler, P Vasina. A method for locating the position of oxide traps responsible for random telegraph signals in submicron MOSFETs. IEEE Trans Electron Dev, 47, 646(2000).
[21] Y C Cheng, H B Chen, M H Han et al. Temperature dependence of electronic behaviors in quantum dimension junctionless thin-film transistor. Nanoscale Res Lett, 9, 1(2014).