High-performance RF Switch in 0.13 μm RF SOI process

Hong Guan; Hao Sun; Junlin Bao; Zhipeng Wang; Shuguang Zhou; Hongwei Zhu

doi:10.1088/1674-4926/40/2/022401

[1] C L Chen, P W Wyatt, D R Yost. Fully depleted SOI RF switch with dynamic biasing. IEEE Radio Frequency Integrated Circuits Symposium, 175(2007).

[2] D Kelly, C Brindle, C Kemerling. The state-of-the-art of silicon-on-sapphire CMOS RF switches. Compound Semiconductor Integrated Circuit Symposium, 200(2005).

[3] S Makioka, Y Anda, K Miyatsuji. Super self-aligned GaAs RF switch IC with 0.25 dB extremely low insertion loss for mobile communication systems. IEEE Trans Electron Devices, 48, 1500(2001).

[4] F J Huang, O Kenneth. A 0.5-μm CMOS T/R switch for 900 MHz wireless applications. IEEE J Solid-State Circuit, 36, 486(2001).

[5] F Gianesello, A Momroy, V Vialla. Highly linear and sub 120 fs R_on × C_off 130 nm RF SOI technology targeting 5G carrier aggregation RF switches and FEM SOC. IEEE Silicon Monolithic Integrated Circuits in RF Systems, 9(2016).

[6] P A Rabbeni, A Joseph. RF SOI: revolutionizing RF system design. Microwave J, 58, 22(2015).

[7] X S Wang, X Wang, F Lu. Concurrent design analysis of high-linearity SP10T switch with 8.5 kV ESD protection. IEEE J Solid-State Circuit, 49, 1927(2014).

[8] X S Wang, X Wang, F Lu. A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV + ESD protection by co-design. Custom Integrated Circuit Conference, 1(2013).

[9] B K Esfeh, M Rack, S Makovejev. A SPDT RF switch small and large signal characteristics on TR-HR SOI substrates. IEEE J Electron Devices Soc, 543(2018).

[10] C Tinella, O Richard, A Cathelin. 0.13 μm CMOS SOI SP6T antenna switch for multi-standard handsets. IEEE Silicon Monolithic Integrated Circuits in RF Systems, 4(2006).

[11] I Song, M K Cho. PNP-based RF switches for the mitigation of single-event transients in a complementary SiGe BiCMOS platform. IEEE Trans Nucl Sci, 65, 391(2017).

[12] M D Wei, R Negra. High-isolation stacked RF switch using dc-lift and feed forward cancellation techniques in standard 65 nm CMOS. IEEE International Symposium, 1(2018).