High-performance RF Switch in 0.13 μm RF SOI process

Hong Guan; Hao Sun; Junlin Bao; Zhipeng Wang; Shuguang Zhou; Hongwei Zhu

doi:10.1088/1674-4926/40/2/022401

Abstract

A high-performance single-pole single-throw (SPST) RF switch for mobile phone RF front-end modules (FEMs) was designed and characterized in a 0.13 μm partially depleted silicon-on-insulator (PD SOI) process. In this paper, the traditional series-shunt configuration design was improved by introducing a suitably large DC bias resistor and leakage-preventing PMOS, together with the floating body technique. The performance of the RF switch is greatly improved. Furthermore, a new R_on × C_off testing method is also proposed. The size of this SPST RF switch is 0.2 mm². This switch can be widely used for present 4G and forthcoming 5G mobile phone FEMs.

1. Introduction

RF front-end modules (FEMs) have become increasingly prominent with the increase in 4G and 5G mobile communication which is required for multi-band and multi-mode applications. The RF switch is the largest demand module in the RF FEM product; its performance directly determines the entire RF transceiver system. Insertion loss and isolation are two major parameters that measure the performance of the RF switch in addition to the linearity requirement (harmonics) and power handling capacity. However, achieving a trade-off among these various parameters is often difficult. Most previous studies on RF switch performance, such as those on insertion loss, isolation, and P_{0.1 dB}, harmonics, are insufficient, since they do not consider the R_on × C_off metrics. Hence, this paper not only focuses on the optimization of the primary RF switch parameters, such as insertion loss, isolation, P_{0.1 dB}, and linearity, but also measures the product R_on × C_off. A high-quality SPST RF switch is designed by improving switch structure and parameter optimization^[1] in a 0.13 μm PD SOI process.

2. RF SOI process

The wireless communication industry has always been interested in integrating a multi-mode multi-band RF switch in one small and low-cost system. Undoubtedly, the RF SOI process is cost effective for RF switches in comparison to other technologies, such as conventional bulk CMOS, silicon-on-sapphire, and GaAs^[2–4].

The low-R_on body-contact (BC) transistor is selected for the RF switch design as it can reduce insertion loss in the case of a large voltage swing and also has high voltage handling capability through device stacking, which can greatly increase linearity, while reduced C_off for improved isolation can also be achieved in the design. Fig. 1 shows inherently small overlap capacitance C_ov and junction capacitance C_j of the transistor while the switch in the off state. R_on is measured from a single transistor; usually we measured I_d @ 2.5 V V_g, 0.05 V V_d, then obtained I_din by normalizing I_d to transistor width. In addition, we obtain C_off from C_ov plus C_j, with C_ov measured @ 0 V V_g, 45 mV 1 MHz AC condition, while C_j is measured @ 0 V V_b, 45 mV 1 MHz AC condition. Eqs. (1) and (2) give the transistor’s R_on and C_off measurement formulas and the figure of merit (FoM) of the RF switch can be obtained by using Eq. (3).

Figure 1.(Color online) Simplified capacitive models.

$ {{{R}}_ {\rm{on}}}\left( {{\rm{ \Omega}}/{ \mu {\rm m}}} \right) = \frac{{{V_ {\rm{d}}}}}{{{I_ {\rm{din}}}}}\left( {I_ {\rm{din}} = \frac{{{{{I}}}}_ {\rm{d}}}{{{W}}}} \right) , $  (1)

${C_ {\rm{off}}}\left( {{\rm fF}/ \mu {\rm m}} \right) = \frac{1}{2}{C_ {\rm{ov}}} + {C_j},$  (2)

${\rm{FOM}}\left( {{\rm{fs}}} \right) = {{{R}}_ {\rm{on}}}{C_ {\rm{off}}}.$  (3)

By ignoring the influence of other capacitances, only the effects of gate-to-source and gate-to-drain on overlap capacitance C_ov are considered, because source-to-body, drain-to-body, and gate-to-body are too small for C_ov,and junction capacitance C_j mainly refers to source-to-body and drain-to-body. As reducing R_on × C_off can improve the performance of linearity (P_{0.1 dB}, harmonic), R_on reduction will be considered first^[5]. R_on reduction for intrinsic FETs is fundamentally achieved through channel length shrink. However, this reduction must be carefully balanced with a corresponding decrease in break down voltage of BVD_ss^[6]. Reducing BVD_ss requires a large FET stack number and chip area. Increased high isolation can be achieved by reducing C_off through optimization of the RF switch transistor layout.

The RF SOI Platform is much more preferable for the RF Switch module due to the excellent R_on × C_off performance; the ideal RF Switch should have much lower R_on in the turned-on state to transmit the RF signal with low insertion loss and high linearity. Furthermore, the RF switch should also have lower parasitic capacitance to block or isolate the unwanted RF signal in the turned-off state to maintain high terminal isolation. In most situations, R_on should be traded off against C_off, it is difficult to improve R_on while maintaining C_off at the same level and vice versa. Therefore, R_on × C_off is a good figure of merit by which to assess the RF SOI Platform performance.

3. Design optimization of RF switch

The most important parameters of the RF switch are insertion loss (IL), isolation (ISO), and power handling capacity measured by P_0.1_dB. Isolation and insertion loss are limited primarily by off-state parasitic capacitance and on-state current leakage. The IL and ISO can be expressed by Eqs. (4) and (5).

${\rm IL} = - 20\log \frac{{{R_ {\rm{o}}}}}{{2{R_0} + {R_ {\rm{on}}}}},$ (4)

${\rm ISO} = - 10\log \frac{{2{R_0}}}{{2{R_0} + \frac{2}{{\omega {C_ {\rm{off}}}}}}}.$ (5)

In commercial mobile phones, the GSM band transmit mode requires a power level at the antenna port as high as 35 dBm at 0.9 GHz and 33 dBm at 1.9 GHz and their maximum output power and maximum peak to peak voltage can be calculated as follows:

${P_ {\rm{watt}}} = {10^{\frac{{35}}{{10}}}}\times0.001 = 3.16\;{\rm W},$ (6)

${V_ {\rm{peak}}} = \sqrt {2{P_ {\rm{watt}}}{Z_0}} = 17.8\;{\rm V},$ (7)

${V_{\max }} = {V_ {\rm{peak}}}\left(1 + \frac{{\rm VSWR - 1}}{{\rm VSWR + 1}}\right) = 28.5\;{\rm V}.$ (8)

From Eqs. (6)–(8), 35 dBm power can be translated into 28.5 V peak voltage for a 4 : 1 VSWR, which requires stacked NFETs with breakdown voltage of 3.3 V in the GSM transmit paths to prevent transistors in the off-state from turning on, which greatly degrades signal linearity.

As shown in Fig. 2, we provide an improved series-shunt configuration by adding a big DC bias resistor and leakage preventing PFET in the schematic to optimize the overall performance of the RF switch. These stacked FETs are used to handle the GSM transmit mode high voltage swing and increase the power handling capability. The gate resistors (R1–R10) are used to improve the linearity of the RF switch while the body resistors are used to improve insertion loss by blocking the current leakage to the ground^{[7, 8]}. The resistors between the source and drain for each stacking transistor are used for voltage division, evenly distributing the transmit above calculated high voltage. The PFET across the gate and body of each NFET is for self-bias to simplify bias design. If the NFET is turned on, then PFET will be turned off and the NFET body will be connected to ground through VB1/VB2; the floating body can offer super-high impedance to minimize IL. If the NFET is turned off and under a negative gate voltage (−2 V), the PFET will be turned on to ensure that the body is close to the negative gate, preventing the RF signal from leaking. Therefore, when an RF signal goes through the switch, the series NFETs (M1–M10) are turned on, which means that the switch is in the closed state and the RF signal can be transmitted or received with low insertion loss. Meanwhile, the shunt NFETs (M21–M30) are turned on in order to increase isolation and ensure the RF switch is totally open without any current leakage ensuring high isolation.

Figure 2.Proposed RF switch.

The optimized insertion loss and isolation of the RF switch should be balanced by selecting the best NFET transistor width. In Figs. 3(a) and 3(b), simulation results are given as the NFET width increases from 1.25 to 3.75 mm. Considering that large transistor width will increase parasitic capacitance and the reduction in insertion loss tends to be less, a 2.5 mm transistor width is selected. A typical value for the gate bias resistance is 50 kΩ. Fig. 4 shows a photomicrograph of the chip with a size of 0.4 × 0.5 mm², including testing RF GSG pads.

Figure 3.(Color online) (a) Simulated IL for varying widths of NFETs at 0.9 and 1.9 GHz. (b) Simulated ISO for varying widths of NFETs at 0.9 and 1.9 GHz.

Figure 4.(Color online) Photomicrograph of RF switch chip.

4. Measurement and discussion

The designed RF switch chip is tested by using a network analyzer through the S-parameter for both insertion loss and isolation. The product of R_on and C_off is actually one of the key merits of the RF switch and a low FoM (120 fs) is given in Fig. 5.

Figure 5.Measured R_on × C_off for RF switch.

Insertion loss and isolation are measured using an Agilent N9020A Network Analyzer, while P_{0.1 dB} and harmonics are measured using an Agilent E4440A PSA Series Spectrum Analyzer. For insertion loss of this RF switch, the measurement bias voltages VB1 and V1 are 0, 2.5 V while VB2 and V2 are −2 V. As shown in Fig. 6, the RF switch exhibits low insertion loss of 0.24/0.34 dB and isolation (Fig. 7) takes on higher values of 28.8/22.4 dB at frequency bands of 0.9/1.9 GHz, respectively. The linearity of the RF switch is analyzed by P_{0.1 dB} and harmonic measurements. The P_{0.1 dB}(Fig. 8) is well beyond 36 dBm, meeting the GSM 900 standard, which dictates that the maximum available power at the antenna should be at least 33 dBm. The 2nd and 3rd harmonics were measured when a body is biased at 0 V and the gate is biased at 2.5 V. Fig. 9 shows another metric of linearity, the 2nd and 3rd order harmonics are lower than −41 at 34 dBm input power.

Figure 6.(Color online) Measured IL for RF switch.

Figure 7.(Color online) Measured ISO for RF switch.

Figure 8.(Color online) Measured P_{0.1 dB} for RF switch.

Figure 9.(Color online) Measured harmonics for RF switch.

Table 1 compares several key parameters with the relevant state-of-the-art RF switches reported. The performance of this SPST RF switch is comparable to that of the RF switch designed in HR SOI^[9], which has more expensive substrate and SiGe BiCMOS^[11], CMOS technology^[12]. Compared with SP10T designed in 0.18 μm SOI^[7] and SP6T with 0.13 μm SOI^[10], this switch has a lower IL in the case of equal P_{0.1 dB}. All of linearity, R_on × C_off, insertion loss, and isolation are considered to achieve good overall performance in the SPST switch. These performances can fully meet the requirements of the present mobile phone RF FEM system for multi-mode and multi-frequency applications.

Table Infomation Is Not Enable

5. Conclusions

A high-performance RF switch with ultra-low insertion loss, high isolation, and linearity is achieved through 0.13 μm RF SOI. The inherent advantages of the SOI process combined with the optimization of the circuit structure significantly improve the performance of the RF switch. Results show a good performance for the SPST RF switch which is used in 4G and 5G mobile phone FEMs and can be used widely in forthcoming 5G technology.

Acknowledgements

This work was supported by the 111 Project (No. B12026).

References

[1] C L Chen, P W Wyatt, D R Yost. Fully depleted SOI RF switch with dynamic biasing. IEEE Radio Frequency Integrated Circuits Symposium, 175(2007).

[2] D Kelly, C Brindle, C Kemerling. The state-of-the-art of silicon-on-sapphire CMOS RF switches. Compound Semiconductor Integrated Circuit Symposium, 200(2005).

[3] S Makioka, Y Anda, K Miyatsuji. Super self-aligned GaAs RF switch IC with 0.25 dB extremely low insertion loss for mobile communication systems. IEEE Trans Electron Devices, 48, 1500(2001).

[4] F J Huang, O Kenneth. A 0.5-μm CMOS T/R switch for 900 MHz wireless applications. IEEE J Solid-State Circuit, 36, 486(2001).

[5] F Gianesello, A Momroy, V Vialla. Highly linear and sub 120 fs R_on × C_off 130 nm RF SOI technology targeting 5G carrier aggregation RF switches and FEM SOC. IEEE Silicon Monolithic Integrated Circuits in RF Systems, 9(2016).

[6] P A Rabbeni, A Joseph. RF SOI: revolutionizing RF system design. Microwave J, 58, 22(2015).

[7] X S Wang, X Wang, F Lu. Concurrent design analysis of high-linearity SP10T switch with 8.5 kV ESD protection. IEEE J Solid-State Circuit, 49, 1927(2014).

[8] X S Wang, X Wang, F Lu. A smartphone SP10T T/R switch in 180-nm SOI CMOS with 8kV + ESD protection by co-design. Custom Integrated Circuit Conference, 1(2013).

[9] B K Esfeh, M Rack, S Makovejev. A SPDT RF switch small and large signal characteristics on TR-HR SOI substrates. IEEE J Electron Devices Soc, 543(2018).

[10] C Tinella, O Richard, A Cathelin. 0.13 μm CMOS SOI SP6T antenna switch for multi-standard handsets. IEEE Silicon Monolithic Integrated Circuits in RF Systems, 4(2006).

[11] I Song, M K Cho. PNP-based RF switches for the mitigation of single-event transients in a complementary SiGe BiCMOS platform. IEEE Trans Nucl Sci, 65, 391(2017).

[12] M D Wei, R Negra. High-isolation stacked RF switch using dc-lift and feed forward cancellation techniques in standard 65 nm CMOS. IEEE International Symposium, 1(2018).