• Journal of Semiconductors
  • Vol. 41, Issue 6, 062401 (2020)
Shizhe Wei1, Haifeng Wu2, Qian Lin3, and Mingzhe Zhang1
Author Affiliations
  • 1School of Microelectronics, Tianjin University, Tianjin 300072, China
  • 2Chengdu Ganide Technology, Chengdu 610073, China
  • 3College of Physics and Electronic Information Engineer, Qinghai University for Nationalities, Xining 810007, China
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    DOI: 10.1088/1674-4926/41/6/062401 Cite this Article
    Shizhe Wei, Haifeng Wu, Qian Lin, Mingzhe Zhang. A 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier[J]. Journal of Semiconductors, 2020, 41(6): 062401 Copy Citation Text show less
    The equivalent AC circuit.
    Fig. 1. The equivalent AC circuit.
    Schematic of proposed PA.
    Fig. 2. Schematic of proposed PA.
    (Color online) Effects of R2 on S-parameter. (a) S11. (b) S21. (c) S22.
    Fig. 3. (Color online) Effects of R2 on S-parameter. (a) S11. (b) S21. (c) S22.
    (Color online) Effects of R2 on output power and PAE (post-layout simulation). (a) Output power. (b) PAE
    Fig. 4. (Color online) Effects of R2 on output power and PAE (post-layout simulation). (a) Output power. (b) PAE
    (Color online) Microphotograph of the stacked PA.
    Fig. 5. (Color online) Microphotograph of the stacked PA.
    (Color online) Photograph of the test system.
    Fig. 6. (Color online) Photograph of the test system.
    (Color online) K-factor and S-parameters.
    Fig. 7. (Color online) K-factor and S-parameters.
    (Color online) Output power and PAE.
    Fig. 8. (Color online) Output power and PAE.
    ParameterRef. [4] Ref. [6] Ref. [7] Ref. [8] This work
    Technology90 nm0.6 μm 0.18 μm 0.18 μm 0.18 μm
    Frequency (GHz)5.2–130.5–8.53.1–91–50.1–1.5
    S11 (dB) < –11< –6< –9< –5< –10.8
    S22 (dB) < –3.9< –9.5< –8< –4< –9.6
    Gain (dB)1461015 – 2022.3 ± 1.5
    OP1dB (dBm) 22.662021
    Power (mW)1810100126
    Peak PAE (%)21.63620
    Area (mm2) 0.45 × 1.551.3 × 2.21.1 × 10.9 × 0.760.58 × 0.76
    Table 1. Performance of Broadband CMOS PAs.
    Pin (dBm) Vds1 (V) Ids1 (mA) Vds2 (V) Ids2 (mA)
    –25475107
    05465106
    25495105
    45535101
    Table 2. Power consumption of each stage.
    Shizhe Wei, Haifeng Wu, Qian Lin, Mingzhe Zhang. A 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier[J]. Journal of Semiconductors, 2020, 41(6): 062401
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