Currently, GaAs pHEMT switches play a more and more important role in RF switching and exhibit excellent performance in modern communication systems^{[1, 2]}. Compared to traditional devices, GaAs pHEMT switches provide lower insertion loss, higher isolation, and a wider work frequency band. As the isolation and insertion loss requirements of switches for different circuits vary, multi-gate structures are also popularly used in designs.

Accurate device modeling is a very important part of the semiconductor industry. For HEMT devices, the related research and literature have become popular, but generally only for common-source structures^[3-11]. However, much less research is related to the modeling of GaAs pHEMT switches^[12-16]. GaAs pHEMT switches are common gate devices with a feature that distinguishes them from other structures. To prevent leakage of the RF signal, GaAs pHEMT switches are connected to a sufficiently large resistor at the gate. The parasitic environment of the GaAs pHEMT switches is different due to the unique structures; thus, the traditional small-signal model extraction method is no longer applicable. A simple topology cannot accurately describe the performance of a device with a high frequency^[12]. The optimization-based extraction method is time consuming^[13]. Several different researches have raised some issues that need to be considered in the modeling of GaAs pHEMTs^[14-16]. The low-frequency dispersion effect due to surface traps has an effect on the gate capacitor, and the pulse method is effective in improving the modeling accuracy^[14]. A significant effect of the precise multi-capacitive current path on the switch model precision has been found^[15]. The gate leakage prevention resistors of the switching device contribute to the extraction of the gate capacitor^[16]. Currently, there are many articles that mention the modeling of switches^[12-16], but the detailed extraction process for a multi-gate structure is not developed.

This paper presents a direct extraction method for GaAs pHEMT switches with a model that can be extended to multi-gate devices. In Section 2, the devices involved in this work and the related measurement instruments are introduced. The extraction process of the external parasitic parameters and intrinsic capacitor is described in detail in Section 3. Section 4 presents a verification of the model and a comparison of the simulated and measured data. Finally, the conclusions of this paper are presented.

The GaAs pHEMT switches employed in this work include one switch with the normal common-gate GaAs pHEMT structure and a GaAs pHEMT switch whose gate is connected with a blocking resistor. In addition, the measured device includes a separate open structure for the extraction of the external parasitic capacitors. This device is grown on a 50 nm thick GaAs substrate as shown in Fig. 1, followed by a GaAs buffer layer to improve the effect of substrate defects of the channel. The channel is formed at the top of the InGaAs layer, and the electrons are provided by the upper AlGaAs layer. Ohmic contacts are created on the uppermost layer.

Fig. 2 shows the layout of the dual-gate GaAs pHEMT switch. The gate length of the GaAs pHEMT switch is 0.5 µm, the total width is 625 μm (125 μm × 5), whose number of fingers is 5 with 125 μm finger width. and the value of the resistor switch connected to the gate is 20 kΩ. The multi-gate device is extended with dual, triple and quadruple gates. An advanced measurement system is used to characterize the considered GaAs pHEMT switches. The instruments in the measurement system include: a Cascade probe station, which can support on-chip testing; an Agilent 4156C DC power supply to provide a specific bias voltage to operate the switch at a specific voltage; and a Keysight vector network analyzer (VNA) for the two-part S parameter measurements for the model extraction and verification at 20 GHz.

In this paper, the intrinsic structure of a multi-gate device can be represented by a series connection of the intrinsic structure of single-gate switches^[14]. A specific circuit is proposed in this work as shown in Fig 3. In this circuit, C_dp and C_sp are the parasitic capacitors due to the package effects, and R_dp and R_sp are the parasitic resistors due to the same effects. R_d, R_s, R_g, L_d, L_s and L_g account for the parasitic resistors and inductors due to the contacts with the drain, source and gate, respectively. Here, C_gd, C_gs and C_ds are the gate-to-drain capacitor, gate-to-source capacitor and drain-to-source capacitor, which are the intrinsic capacitors. R_gd and R_gs are chosen to control the voltage of C_gs and C_gd, which can improve the accuracy of parameter extraction at different voltages. R_ds represents the channel resistors between the drain and the source. R_G is a large resistor (20 kΩ) that can prevent the leakage of the RF signal. The source resistance to the inter-gate region R_m, the gate-to-gate coupling capacitor C_gg*, and the external capacitor between the drain and source C_ds are introduced.

It is of great importance to accurately extract the external parasitic parameters in the modeling of small-signal models. An incomplete or exaggerated removal of the extrinsic capacitors influences the subsequently extracted elements and thus introduces errors. From the paper^[17], we know that the extraction of extrinsic parasitic capacitors is achieved mainly with the following two mainstream extraction methods: (1) the traditional cold-FET pinch extraction method^[18] and (2) the open structure method^[19]. Since the open structure has been designed, the open de-embedding method is used to extract the parasitic parameters. For the parasitic capacitor, the open structure has the same size as that of the extraction switch device. C_dp and C_sp are the parasitic capacitors of the pad to the ground, and C_dsp represents the parasitic capacitor between the two sides of the pad.

The imaginary part of the Y-parameters can be expressed with the following formula:

$ {\rm{Imag}}\left( {{Y_{11}}} \right) = j\omega \left( {{C_{{\rm{dp}}}} + {C_{{\rm{dsp}}}}} \right), $  (1)

$ {\rm{Imag}}\left( {{Y_{12}}} \right) = {\rm{Imag}}\left( {{Y_{21}}} \right) = - j\omega {C_{{\rm{dsp}}}}, $  (2)

$ {\rm{Imag}}\left( {{Y_{22}}} \right) = j\omega \left( {{C_{{\rm{sp}}}} + {C_{{\rm{dsp}}}}} \right), $  (3)

$ {C_{{\rm{dp}}}} = {\rm{Imag}}\left( {{Y_{11}} + {Y_{12}}} \right)/\omega , $  (4)

$ {C_{{\rm{sp}}}} = {\rm{Imag}}\left( {{Y_{22}} + {Y_{12}}} \right)/\omega , $  (5)

$ {C_{{\rm{dsp}}}} = - {\rm{Imag}}\left( {{Y_{12}}} \right)/\omega . $  (6)

The extracted parameters via Eqs. (1)–(6) are shown in Fig. 4.

After de-embedding the effect of the pad parasitic capacitors, the other parasitic parameters can be extracted from the Z-parameters under the condition (V_ds = 0 V, V_gs = 0 V). The equivalent topology is shown in Fig. 5. R_d, R_s and R_g are the parasitic resistors. L_d, L_s and L_g represent the parasitic inductors. R_ds is the channel resistors, and C_b represents the effect of the gate capacitors, including C_gs, C_gd and C_gg*.

The Z-parameters can be expressed as the following formula:

$ {Z_{11}} = {R_{\rm{d}}} + \frac{{{R_{\rm{ds}}}}}{2} + {R_{\rm{g}}} + {R_{\rm{G}}} + j\left[\omega \left( {{L_{\rm{g}}} + {L_{\rm{d}}} - \frac{1}{{\omega {C_{\rm{b}}}}}} \right)\right], $  (7)

$ {Z_{12}} = {Z_{21}} = {R_{\rm{g}}} + {R_{\rm{G}}} + j\left[ {\omega \left( {{L_{\rm{g}}} - \frac{1}{{\omega {C_{\rm{b}}}}}} \right)} \right], $  (8)

$ {Z_{22}} = {R_{\rm{s}}} + \frac{{{R_{\rm{ds}}}}}{2} + {R_{\rm{g}}} + {R_{\rm{G}}} + j\left[\omega \left( {{L_{\rm{g}}} + {L_{\rm{s}}} - \frac{1}{{\omega {C_{\rm{b}}}}}} \right)\right]. $  (9)

Since the blocking resistor R_G = 20 kΩ prevents the leakage of RF signal, L_g and R_g can be ignored. The extracted parameters are shown in Fig. 6.

After all of the external parasitic parameters have been removed, the intrinsic parameters can be accurately extracted. However, the gate is equivalent to an open circuit to the ground because the resistor R_G prevents the leakage of RF signal. For this case, the equivalent circuit is shown in Fig. 7.

Because the depletion layer under the gate is symmetric, it can be assumed that:

$ {C_{{\rm{gd}}}} = {C_{{\rm{gs}}}} = {C_{\rm{g}}}, \quad {R_{\rm{gd}}} = {R_{\rm{gs}}} = {R_{\rm{gds}}}. $  (10)

R_m is small enough to be ignored. At this time, the Y-parameters are expressed as follows:

$ {Y_{11}} = \frac{1}{{{R_{\rm{ds}}}}} + j\omega {C_{\rm{ds}}} + {Y_{\rm{tmp}}}, $  (11)

$ {Y_{12}} = {Y_{21}} = - \frac{1}{{{R_{\rm{ds}}}}} - j\omega {C_{\rm{ds}}} - {Y_{\rm{tmp}}}, $  (12)

$ {Y_{22}} = \frac{1}{{{R_{\rm{ds}}}}} + j\omega {C_{\rm{ds}}} + {Y_{\rm{tmp}}}. $  (13)

Y_tmp represents the intermediate variable of the admittance, and the specific form is as follows:

$ {Y_{\rm{tmp}}} = \dfrac{1}{{2{R_{\rm{gds}}} + \dfrac{1}{{2j\omega {C_{\rm{g}}}}} + \dfrac{{\left( {2{R_{\rm{gds}}} + \dfrac{1}{{2j\omega {C_{\rm{g}}}}}} \right)\dfrac{1}{{j\omega C_{\rm{g{g}}^*}}}}}{{\left( {2{R_{\rm{gds}}} + \dfrac{1}{{2j\omega {C_{\rm{g}}}}}} \right) + \dfrac{1}{{j\omega C_{\rm{g{g}}^*}}}}}}}. $  (14)

It can be obtained that:

$ {Y_{11}} = - {Y_{12}} = - {Y_{21}} = - {Y_{22}}. $  (15)

Obviously, the intrinsic parameters cannot be extracted. Because the channel carrier under the gate is depleted in the deep-off-state, the intrinsic capacitors are mainly the fringe capacitance. The intrinsic capacitors (C_gs, C_gd and C_ds) should be extracted from the GaAs pHEMT switch without the gate resistor R_G. The device behaves as a common-gate structure of a pHEMT. With the effect of the inductor being ignored at low frequencies, considering only the imaginary part of the Y-parameter, the equivalent circuit is expressed as follows:

$ {\rm{Imag}}\left( {{Y_{11}}} \right) = j\omega \left( {{C_{\rm{gd}}} + {C_{\rm{ds}}}} \right), $  (16)

$ {\rm{Imag}}\left( {{Y_{12}}} \right) = {\rm{Imag}}\left( {{Y_{21}}} \right) = - j\omega {C_{\rm{ds}}}, $  (17)

$ {\rm{Imag}}\left( {{Y_{22}}} \right) = j\omega \left( {{C_{\rm{gs}}} + {C_{\rm{ds}}}} \right). $  (18)

The extracted results via Eqs. (16)–(18) are shown in Fig. 8.

Under the same conditions, the channel resistors are extracted by the real part of the Y-parameter:

$ {\rm{Real}}\left( {{Y_{21}}} \right) = - \frac{1}{{{R_{\rm{ds}}}}}. $  (19)

It is worth mentioning that the gate-to-gate capacitor C_gg* is adjusted to fit the off-state capacitor values. After all of the external parasitic parameters have been removed, considering only the imaginary part of the Y-parameter at low frequencies, the equivalent topology of the capacitors can be expressed as Fig. 9. The gate is equivalent to an open circuit to the ground. In the above extraction process, C_gs= C_gd= C_g is verified. Therefore, the imaginary part of Y₁₁ can be derived as fellow:

$ {\rm{Imag}}\left( {{Y_{12}}} \right) = - j\omega \left( {{C_{\rm{ds}}} + \frac{{\displaystyle\frac{1}{2}C_{\rm{g*}}\left( {\displaystyle\frac{1}{2}C_{\rm{g}} + C_{\rm{g{g}*}}} \right)}}{{\displaystyle\frac{1}{2}C_{\rm{g}} + \left( {\displaystyle\frac{1}{2}C_{\rm{g}} + C_{\rm{g{g}*}}} \right)}}} \right). $  (20)

C_gg* can be accurately extracted because C_g and C_ds have been extracted from common-gate HEMTs.

Since all the extrinsic parasitic parameters are accurately extracted, the extracted intrinsic parameters hardly change with frequency. Table 1 summarizes the selection of the extracted values for the on and off states. So far, all the parameters of the dual-gate switch are extracted completely, and the verification of the model is discussed in the next section.

The above extraction method is applied to extract the parameters of a GaAs HEMT switch with a measurement frequency range extending from 100 MHz to 20 GHz. Devices with dual, triple and quadruple gates are verified, considering a gate length of 0.5 µm and a gate total width of 625 µm (125 µm × 5). The fitting results of the GaAs HEMT switches are shown in Table 2.

Fig. 10 shows a comparison of the S-parameters between the simulation and the measurement of the on and off states in Smith charts. The agreements between the measured and simulated data are excellent over a wide frequency range.

The error formulations can be expressed using the following equations:

$ e = \dfrac{{\left| {{S_{\rm{simu}}}\left( i \right) - {S_{\rm{meas}}}\left( i \right)} \right|}}{{\sqrt {\dfrac{{\sum\nolimits_n {{{\left( {{S_{\rm{meas}}}\left( i \right)} \right)}^2}} }}{n}} }}, $  (21)

where S_simuand S_meas represent the simulated and measured data sets, and n is the number of data points included in each data set. Table 3 shows the error percentage of different devices. The verification and accuracy are guaranteed. The percentage errors between the measured and simulated data are within 3%. Table 3 shows the different errors of each device.

The insertion loss and isolation results of the GaAs pHEMT multi-gate switch with a gate total width of 5 × 125 μm are shown in Fig. 11. The results of the modeling procedure fit the measurements well up to 20 GHz.

A small-signal equivalent circuit for multi-gate GaAs pHEMTs in RF switching mode is proposed, and a direct extraction method is developed. By comparing the measured S-parameters with the model simulation results, it is found that the model provides high accuracy and strong reliability. Good fitting results for different gates also confirm the scalability of the extraction method. This extraction method can be applied to multi-gate GaAs pHEMT switch devices.