Fast-transient techniques for high-frequency DC–DC converters

Lin Cheng; Kui Tang; Wang-Hung Ki; Feng Su

doi:10.1088/1674-4926/41/11/112402

[1]

[2] K L Wong, T Rahal-Arabi, M Ma et al. Enhancing microprocessor immunity to power supply noise with clock-data compensation. IEEE J Solid-State Circuits, 41, 749(2006).

[3] K A Bowman, S Raina, J T Bridges et al. A 16 nm all-digital auto-calibrating adaptive clock distribution for supply voltage droop tolerance across a wide operating range. IEEE J Solid-State Circuits, 51, 8(2015).

[4] S T Kim, Y C Shih, K Mazumdar et al. Enabling wide autonomous DVFS in a 22 nm graphics execution core using a digitally controlled fully integrated voltage regulator. IEEE J Solid-State Circuits, 51, 18(2016).

[5] J Roh. High-performance error amplifier for fast transient DC–DC converters. IEEE Trans Circuits Syst II, 52, 591(2005).

[6] C Y Hsieh, K H Chen. Adaptive pole-zero position (APZP) technique of regulated power supply for improving SNR. IEEE Trans Power Electron, 23, 2949(2008).

[7] J S Chang, H S Oh, Y H Jun et al. Fast output voltage-regulated PWM buck converter with an adaptive ramp amplitude control. IEEE Trans Circuits Syst II, 60, 712(2013).

[8] Y Y Mai, P K T Mok. A constant frequency output-ripple-voltage-based buck converter without using large ESR capacitor. IEEE Trans Circuits Syst II, 55, 748(2008).

[9] S J Wang, Y H Lee, Y C Lai et al. Quadratic differential and integration technique in V² control buck converter with small ESR capacitor. 2009 IEEE Custom Integrated Circuits Conference, 211(2009).

[10] Y S Hwang, A Liu, Y B Chang et al. A high-efficiency fast-transient-response buck converter with analog-voltage-dynamic-estimation techniques. IEEE Trans Power Electron, 30, 3720(2015).

[11] J J Chen, Y S Hwang, H H Chai et al. A sub-1-μs ultrafast-response buck converter with improved analog-voltage-dynamic-estimation techniques. IEEE Trans Ind Electron, 65, 1695(2018).

[12] J Cortes, V Svikovic, P Alou et al. V¹ concept: Designing a voltage-mode control as current mode with near time-optimal response for buck-type converters. IEEE Trans Power Electron, 30, 5829(2015).

[13] S Y Huang, K Y Fang, Y W Huang et al. Capacitor-current-sensor calibration technique and application in a 4-phase buck converter with load-transient optimization. 2016 IEEE Int Solid-State Circuits Conf ISSCC, 228(2016).

[14] R Redl, B P Erisman, Z Zansky. Optimizing the load transient response of the buck converter. APEC '98 Thirteenth Annual Applied Power Electronics Conference and Exposition, 170(1998).

[15] K W Yao, M Xu, Y Meng et al. Design considerations for VRM transient response based on the output impedance. IEEE Trans Power Electron, 18, 1270(2003).

[16] F Su, W H Ki. Digitally assisted quasi-V² hysteretic buck converter with fixed frequency and without using large-ESR capacitor. 2009 IEEE International Solid-State Circuits Conference, 446(2009).

[17] M P Chan, P K T Mok. A monolithic 2^nd-order boundary controller for buck converter with fast transient response. 2010 IEEE Asia Pacific Conference on Circuits and Systems, 468(2010).

[18] P F Li, D Bhatia, L Xue et al. A 90–240 MHz hysteretic controlled DC–DC buck converter with digital phase locked loop synchronization. IEEE J Solid-State Circuits, 46, 2108(2011).

[19] M P Chan, P K T Mok. A monolithic digital ripple-based adaptive-off-time DC–DC converter with a digital inductor current sensor. IEEE J Solid-State Circuits, 49, 1837(2014).

[20]

[21] S H Chien, T H Hung, S Y Huang et al. A monolithic capacitor-current-controlled hysteretic buck converter with transient-optimized feedback circuit. IEEE J Solid-State Circuits, 50, 2524(2015).

[22]

[23] L Cheng, Y G Liu, W H Ki. A 10/30 MHz fast reference-tracking buck converter with DDA-based type-III compensator. IEEE J Solid-State Circuits, 49, 2788(2014).

[24]

[25] R Shrestha, R van der Zee, A de Graauw et al. A wideband supply modulator for 20 MHz RF bandwidth polar PAs in 65 nm CMOS. IEEE J Solid-State Circuits, 44, 1272(2009).

[26] P Y Wu, P K T Mok. A two-phase switching hybrid supply modulator for RF power amplifiers with 9% efficiency improvement. IEEE J Solid-State Circuits, 45, 2543(2010).

[27] C J Shih, K Y Chu, Y H Lee et al. A power cloud system (PCS) for high efficiency and enhanced transient response in SoC. IEEE Trans Power Electron, 28, 1320(2013).

[28] Y G Liu, C C Zhan, W H Ki. A fast-transient-response hybrid buck converter with automatic and nearly-seamless loop transition for portable applications. 2012 Proceedings of the ESSCIRC (ESSCIRC), 165(2012).

[29] Y Zhang, D S Ma. A fast-response hybrid SIMO power converter with adaptive current compensation and minimized cross-regulation. IEEE J Solid-State Circuits, 49, 1242(2014).

[30] K I Wu, B T Hwang, C C P Chen. Synchronous double-pumping technique for integrated current-mode PWM DC–DC converters demand on fast-transient response. IEEE Trans Power Electron, 32, 849(2017).

[31] J Sankman, M K Song, D S Ma. A 40-MHz current-mode hysteretic controlled switching converter with digital push-pull current pumping technique for high performance microprocessors. Technical Papers of 2014 International Symposium on VLSI Design, Automation and Test, 1(2014).

[32] L Cheng, W H Ki. 10.6 A 30 MHz hybrid buck converter with 36mV droop and 125ns 1% settling time for a 1.25A/2ns load transient. 2017 IEEE Int Solid-State Circuits Conf ISSCC, 188(2017).

[33] C Huang, P K T Mok. An 84.7% efficiency 100-MHz package bondwire-based fully integrated buck converter with precise DCM operation and enhanced light-load efficiency. IEEE J Solid-State Circuits, 48, 2595(2013).

[34] E Sackinger, W Guggenbuhl. A versatile building block: The CMOS differential difference amplifier. IEEE J Solid-State Circuits, 22, 287(1987).

[35] L Cheng, W H Ki, F Yang et al. Predicting subharmonic oscillation of voltage-mode switching converters using a circuit-oriented geometrical approach. IEEE Trans Circuits Syst I, 64, 717(2017).

[36] Y Okuma, K Ishida, Y Ryu et al. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-μA quiescent current in 65nm CMOS. IEEE Custom Integrated Circuits Conference, 1(2010).

[37] M Onouchi, K Otsuga, Y Igarashi et al. A 1.39-V input fast-transient-response digital LDO composed of low-voltage MOS transistors in 40-nm CMOS process. IEEE Asian Solid-State Circuits Conference, 37(2011).

[38] F Yang, P K T Mok. A 0.6–1V input capacitor-less asynchronous digital LDO with fast transient response achieving 9.5b over 500mA loading range in 65-nm CMOS. ESSCIRC Conference 2015: 41st European Solid-State Circuits Conference (ESSCIRC), 180(2015).

[39] H W Huang, K H Chen, S Y Kuo. Dithering skip modulation, width and dead time controllers in highly efficient DC–DC converters for system-on-chip applications. IEEE J Solid-State Circuits, 42, 2451(2007).