Researching | Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD

Journals >Journal of Semiconductors >Volume 45 >Issue 3 >Page 032501 > Article

Journal of Semiconductors
Vol. 45, Issue 3, 032501 (2024)

Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD

Nicolò Zagni^1、*, Manuel Fregolent^2、**, Andrea Del Fiol², Davide Favero², Francesco Bergamin², Giovanni Verzellesi^3、4, Carlo De Santi², Gaudenzio Meneghesso², Enrico Zanoni², Christian Huber⁵, Matteo Meneghini², and Paolo Pavan¹

Author Affiliations

¹Department of Engineering “Enzo Ferrari”, University of Modena and Reggio Emilia, Modena 41125, Italy

²Department of Information Engineering, University of Padova, Padova 35131, Italy

³Department of Sciences and Methods for Engineering (DISMI), University of Modena and Reggio Emilia, Reggio Emilia 42122, Italy

⁴EN & TECH Center, University of Modena and Reggio Emilia, Reggio Emilia 42122, Italy

⁵Advanced Technologies and Micro Systems Department, Robert Bosch GmbH, Renningen 71272, Germany

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DOI: 10.1088/1674-4926/45/3/032501 Cite this Article

Nicolò Zagni, Manuel Fregolent, Andrea Del Fiol, Davide Favero, Francesco Bergamin, Giovanni Verzellesi, Carlo De Santi, Gaudenzio Meneghesso, Enrico Zanoni, Christian Huber, Matteo Meneghini, Paolo Pavan. Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD[J]. Journal of Semiconductors, 2024, 45(3): 032501 Copy Citation Text

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References

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[4] N Zagni, A Chini, F M Puglisi et al. “hole redistribution” model explaining the thermally activated RON stress/recovery transients in carbon-doped AlGaN/GaN power MIS-HEMTs. IEEE Trans Electron Devices, 68, 697(2021).

[5] M Cioni, N Zagni, F Iucolano et al. Partial recovery of dynamic RON versus OFF-state stress voltage in p-GaN gate AlGaN/GaN power HEMTs. IEEE Trans Electron Devices, 68, 4862(2021).

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[8] K Ohnishi, S Kawasaki, N Fujimoto et al. Vertical GaN p+-n junction diode with ideal avalanche capability grown by halide vapor phase epitaxy. Appl Phys Lett, 119, 152102(2021).

[9] Z L Bian, K Zeng, S Chowdhury. 2.8 kV avalanche in vertical GaN PN diode utilizing field plate on hydrogen passivated P-layer. IEEE Electron Device Lett, 43, 596(2022).

[10] J Liu, M Xiao, Y Zhang et al. 1.2 kV vertical GaN fin JFETs with robust avalanche and fast switching capabilities, 23.2, 1(2021).

[11] K Mukherjee, C De Santi, M Borga et al. Challenges and perspectives for vertical GaN-on-Si trench MOS reliability: From leakage current analysis to gate stack optimization. Materials, 14, 2316(2021).

[12] E B Treidel, O Hilt, V Hoffmann et al. On the conduction properties of vertical GaN n-channel trench MISFETs. IEEE J Electron Devices Soc, 9, 215(2021).

[13] K Mukherjee, C De Santi, M Borga et al. Use of bilayer gate insulator in GaN-on-Si vertical trench MOSFETs: Impact on performance and reliability. Materials, 13, 4740(2020).

[14] K Dannecker, J Baringhaus. Fully vertical gallium nitride trench MOSFETs fabricated with metal-free gate first process. J Vac Sci Technol B, 39, 032204(2021).

[15] M Henn, C Huber. Impact of gate dielectric deposition temperature on p-type inversion channel MOSFETs fabricated on GaN-on-Si, 1(2022).

[16] P Pavan, N Zagni, F M Puglisi et al. The impact of interface and border traps on current–voltage, capacitance–voltage, and split-CV mobility measurements in InGaAs MOSFETs. Phys Status Solidi A, 214, 1600592(2017).

[17] A Guo, J A del Alamo. Unified mechanism for positive- and negative-bias temperature instability in GaN MOSFETs. IEEE Trans Electron Devices, 64, 2142(2017).

[18] T L Wu, J Franco, D Marcon et al. Toward understanding positive bias temperature instability in fully recessed-gate GaN MISFETs. IEEE Trans Electron Devices, 63, 1853(2016).

[19] P Lagger, M Reiner, D Pogany et al. Comprehensive study of the complex dynamics of forward bias-induced threshold voltage drifts in GaN based MIS-HEMTs by stress/recovery experiments. IEEE Trans Electron Devices, 61, 1022(2014).

[20] M Fregolent, A Del Fiol, C De Santi et al. Threshold voltage instability in SiO2-gate semi-vertical GaN trench MOSFETs grown on silicon substrate. Microelectron Reliab, 150, 115130(2023).

[22] D K Schroder. Oxide and interface trapped charges, oxide thickness. John Wiley & Sons, Inc., 319(2005).

[23] S M Sze, K K Ng. Physics of semiconductor devices. John Wiley & Sons, Inc.(2006).

[24] M Z Yu, S McNab, I Al-Dhahir et al. Extracting band-tail interface state densities from measurements and modelling of space charge layer resistance. Sol Energy Mater Sol Cells, 231, 111307(2021).

[25] L Selmi, E Caruso, S Carapezzi et al. Modelling nanoscale n-MOSFETs with III-V compound semiconductor channels: From advanced models for band structures, electrostatics and transport to TCAD, 13.4, 1(2018).

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Nicolò Zagni, Manuel Fregolent, Andrea Del Fiol, Davide Favero, Francesco Bergamin, Giovanni Verzellesi, Carlo De Santi, Gaudenzio Meneghesso, Enrico Zanoni, Christian Huber, Matteo Meneghini, Paolo Pavan. Physical insights into trapping effects on vertical GaN-on-Si trench MOSFETs from TCAD[J]. Journal of Semiconductors, 2024, 45(3): 032501

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