Fig. 1. (Color online) (a) Schematic 2-D view of the pseudo-vertical GaN-on-Si TMOS under study in this work. (b) TEM image of a FIB lamella taken from the gate trench.

Fig. 2. HRTEM image at 820 Kx magnification of the gate interface in the channel region on the etched sidewall for device B.

Fig. 3. (Color online) Experimentally measured I_D−V_GS of device A (a) and B (b). Continuous lines with squares (dashed lines with circles) are the forward and backward sweeps, respectively.

Fig. 4. (Color online) V_T time evolution during (a) stress and (b) recovery experiments on device B. Different stress voltages (V_GS,STR) were applied (see legend), whereas the recovery voltage (V_GS,REC) was always 0 V.

Fig. 5. (Color online) V_T time evolution during (a) stress (V_GS,STR = 30 V) and (b) recovery (V_GS,REC = 0 V) experiments on device A and different temperatures (see legend). No clear dependence of V_T shift on temperature was found.

Fig. 6. (Color online) (a) Interface and (b) border trap densities vs trap energy (E_T) referred to the conduction band edge of GaN (E_C) employed in the simulations of device A (for device B, all parameters were the same except for the concentrations, see Table 1). E_CNL in (a) indicates the assumed charge neutrality level that discriminates between acceptor-like and donor-like interface traps^[22]. Border traps are only acceptor states.

Fig. 7. (Color online) Simulated I_D−V_GS of device A (a) and B (b). Continuous (dashed) lines are the forward and backward sweeps, respectively.

Fig. 8. (Color online) (a) Simulated band diagram (device B) plotted along the lateral dimension perpendicular to the vertical current flow for different V_GS (see legend). (b) Corresponding trapped charge in border traps (n_BT) in the gate oxide (SiO₂) and free electron density (n) in the channel (GaN).

Fig. 9. (Color online) (a) Simulated band diagram (device B) plotted along the lateral dimension perpendicular to the vertical current flow for different V_GS (see legend). (b) Corresponding trapped charge in border traps (n_BT) in the gate oxide (SiO₂) and free electron density (n) in the channel (GaN).

Fig. 10. (Color online) Hysteresis in the I_D−V_GS (see text for definition) of device A and B. Both experimental data and simulation results are shown. Dashed lines are linear fitting of data points. The ≈75% hysteresis reduction at V_GS,max = 40 V of device B compared to A is reproduced by simulations by reducing oxide trap concentration by the same amount.

Fig. 11. (Color online) Sensitivity of H to border trap density (D_BT) with the simulation setup calibrated on device B. The experimental data points at V_GS,max = 40 V are shown for reference.

Fig. 12. (Color online) Sensitivity of SS (obtained on the upward sweep) to interface trap density (D_IT) with the simulation setup calibrated on device B. The experimental data points at V_GS,max = 40 V are shown for reference. The asymptotic theoretical limit (i.e., for a trap-free interface determined only by the depletion capacitance, C_D, and oxide capacitance, C_ox) is also indicated.

Table 1. Trap-related simulation parameters (Device A/Device B).