Abstract
1. Introduction
A conventional MOSFET maintains its performance beyond 100 nm. Several adverse effects arise due to reduction in channel length reduction depending on scaling trends[
In this paper, a comparison is made among different advance MOSFET structures on the basis of their ON and OFF-state performance. The ON and OFF-state performance are the deciding factor in future scaling trends of new transistor structures. The design of MOSFET structures also depends on different applications such as digital circuit, memory, analog/RF and biomedical applications. The paper describes application based MOSFET designs by exploring DC and AC performance parameters. Several MOSFET designs are implemented to check their circuit performance using circuit simulators available in TCAD tool. Such a prefabrication transistor structure and circuit design analysis plays an important role in achieving the desired performance and also to reduce failure or defect in the fabricated sample.
2. Performance parameter
In general, the MOSFET structures are evaluated on the basis of their subthreshold performance and analog/RF performance. The important MOSFET parameters are needed to be discussed before any comparison among different MOSFET structures.
2.1. Subthreshold performance parameters
The region of operation before MOSFET channel inversion is known as the subthreshold region. The subthreshold parameters are a deciding factor to obtain a desired and reliable MOSFET performance.
2.1.1. Threshold voltage
The minimum amount of gate to source voltage required for channel inversion is known as MOSFET threshold voltage (VT). The value of threshold voltage depends mainly on surface potential which is the voltage of MOSFET capacitor surface (top layer of polysilicon or metal above the oxide) and voltage in the bulk of MOSFET.
2.1.2. OFF-state current
When the voltage of the gate is less than the threshold voltage the MOSFET is considered to be in OFF-state. However, in OFF-state there is a flow of current due to minority charge carriers between the drain and source. This current is known as subthreshold current.
2.1.3. ON-state current
When the voltage of the gate is more than the threshold voltage of the MOSFET. The MOSFET is said to be in ON-state. The flow of current in this state is known as ON current denoted by Ion. The movement of electrons takes place from source to drain.
2.1.4. DIBL (drain induced barrier lowering)
It is a short channel effect in which threshold voltage reduces originally at high drain voltage. When the length of the channel is short drain it is close enough to the gate, at high drain voltage the bottleneck opens and the transistor turns on prematurely. The value of DIBL should be as low as possible to obtain ideal output characteristic of MOS transistors reducing threshold voltage variations due to drain field effect on channel potential.
2.1.5. Subthreshold slope (SS)
In the subthreshold region, the gate terminal controls the drain current and the current is exponentially decreased. The slope of the drain current plot and gate voltage with drain, bulk and source voltages fixed gives subthreshold slope. A suitable value of subthreshold slope (~60 mV/decade) is required to limit the heating effect in short channel devices. The subthreshold slope can be expressed as:
2.2. Analog/RF performance parameters
The analog and RF performance mainly depends on transconductance, transistor capacitances, stability factor and cutoff frequency, etc.
2.2.1. Transconductance
Transconductance is the ratio of drain current variation with respect to the gate voltage of transistor over a small interval of time in the drain current versus gate voltage curve. It is represented as gm[
2.2.2. Junction capacitance
Due to the depletion of charge between the source/drain and substrate the junction capacitances in MOSFET is formed. The charged depletion is changed according to the source/drain voltage. When the voltage of the gate exceeds the threshold voltage there is a formation of the channel at the surface. The junction capacitances are deciding factors for small signal analysis of transistor in RF range of frequencies.
2.2.3. Stability factor
The stability factor (K) mainly depends on two-port equivalent circuit parameters of MOS transistors. It decides the conditional or unconditional stability of transistors in RF range of frequencies. The stability factor can be expressed as[
Here, Y11 and Y22 are input and output admittance parameters at port 1 and 2 respectively. The Y12 and Y21 are called as transfer admittances.
2.2.4. Critical frequency
The critical frequency (fk) is essential for a small signal transistor model and also important to maintain a suitable AC transistor gain and frequency bandwidth. The critical frequency can be calculated at stability factor K= 1. The critical frequency mainly depends on MOSFET capacitance (Cgs, Cgd, and Cds etc.) and other parasitic capacitances. The critical frequency can be expressed as[
Here, fT, gds, Rds and Rgs are the frequency at unity gain, output conductance, drain to source and gate to source resistances respectively. Also, the M and N values are calculated in terms of Cgs and Cgd respectively.
3. Device structure and dimensions
Sarkar et al.[
Figure 1.TM-DG MOSFET structure.
The material of the gate having the larger work function in place close to the source and the material which is having the lesser work function is placed close to the drain. Polysilicon gates have depletion width of polysilicon and penetration effect of dopant so metal gates are used. The thickness of the Si film is 10 nm and SiO2 is 2 nm. The concentration of dopant of the source and drain is considered to be 1020 cm–3. The ratio of the length of the three material is taken as (L1 : L2 : L3 = 1 : 1 : 0). The doping concentration of the p substrate is taken as 1016 cm–3. Djeffal et al.[
Figure 2.GAAJ MOSFET with S/D extensions regions.
By including the heavily doped extensions the drain current improves. The GAAJ MOSFET having extensions has high current when compared to conventional GAAJ. The highly doped regions have increased ion current magnitude by 70%. Abhinav et al.[
Figure 3.(Color online) n-type JLDG MOSFET structure.
The dimensions of device parameters and gate work function is 5.2 eV, the thickness of front gate oxide is 1 nm, the thickness of back gate is 1 nm, the thickness of silicon substrate 5 nm, doping concentration Nd is 3 × 1019 cm–3, length of the channel L is 20 nm. Ouruji et al.[
Figure 4.(Color online) Structure of DSBO-SOI MOSFET.
Ajay et al.[
Figure 5.JL DG MOSFET for underlapping at the source end of the channel region.
Figure 6.JL DG MOSFET for underlapping at the drain end of the channel region.
Kwon et al.[
Figure 7.(Color online) Structure of silicon-based MOSFET.
The device parameters are the length of gate given as 100 nm, thickness gate oxide is 3 nm, bottom oxide thickness is 10 nm, width of barrier is 10 nm, depth of barrier 75 nm, drain and source doping and substrate are 1 × 1020 and 1 × 1017 cm–3, respectively. Kumar et al.[
Figure 8.(Color online) Design of BP JL RC MOSFET.
Djeffal et al.[
Figure 9.Structure of DMSG MOSFET.
The device parameters are Na is 1015 cm–3, drain and source doping is 1020 cm–3, the length L is 10 nm, the thickness of oxide is 2 nm, silicon thickness is 10 nm, L1 and L2 is L/2.
Pathak et al.[
Figure 10.(Color online) Structure of an n-type GC-DMGJLT.
Ajay et al.[
Figure 11.(Color online) Junctionless MOSFET with a cavity for detecting biomolecules.
The dimensions of the device are tbio = 9 nm, tox1 = 1 nm, tsi = 10 nm, doping of the source, drain and channel is 1 ×1025 m–3. Length of the cavity is L1 and L3 is 25 nm, and L3 length of the oxide Al2O3 is 50 nm. Pang et al.[
Figure 12.Structure of a pocket n-MOSFET.
The device parameters are channel length which is 0.1 μm, the thickness of oxide is 4 nm, the junction depth (rj) is 0.06 μm, the doping concentration of the pocket (NP) is 1.906 × 1018 cm–3 and doping concentration in the center region (Nc) is 2.175 × 1017 cm–3, length of the pocket (LP) is 0.024 μm. Orouji et al.[
Figure 13.Structure of EJ-SOI MOSFET.
The device parameters given are doping of silicon thin layer is 6 × 1016 cm–3, source and drain doping is 5 × 1019 cm–3, the side gates work function is 4.7 eV, the main gate work function is 4.9 eV, thickness of silicon thin layer is 50 nm, thickness of buried oxide is 500 nm, thickness of gate oxide is 2 nm, thickness of barrier diffusion layer is 2 nm, length of main gate is 50 nm and length of total side gate is 50 nm. Pal et al.[
Figure 14.Design of cylindrical surrounding gate MOSFET using dual material.
The work function of gold (Au ΦM1 4.8 eV), work function of cadmium (Cd) is 4.0 eV. The channel doping of p-type is 6 × 1016 cm–3, n+ source and drain doping region is 5 ×1019 cm–3. Chebaki et al.[
Figure 15.Double Gate junctionless MOSFET with extensions and engineering of gate material.
The parameters of the devices are doping concentration Nd is 5 × 1018 cm–3, doping of the extension is 5 × 1019 cm–3, thickness of silicon tSi is 10 nm, L is 100 nm, L1 and L2 is L/2, the metal (M1) work function is 5.1 eV, metal (M2) work function is 4.5 eV. Wang et al.[
Figure 16.(Color online) Junctionless MOSFET with asymmetric gate (AG-JL MOSFET).
The structure parameters are an oxide (HfO2) with EOT 1 nm, channel doping is 1 × 1019 cm–3, length of gate is 20 nm, thickness of silicon is 6 nm. Kumar et al.[
Figure 17.Structure of recessed channel MOSFET with transparent gate.
The length of the channel (Lg) is 30 nm, width of the device is 200 nm, depth of the groove is 38 nm, junction depth of source and drain is 30 nm, Negative junction depth (NJD) is 10 nm, doping of the substrate (Na) is 1 × 1016 cm–3, doping of source and drain (Nd) is 1 × 1019 cm–3, thickness of physical oxide (tox) is 2 nm. SiO2 permittivity εox is 3.9, gate to source voltage (Vgs) is 0.7 V, drain to source voltage (Vds) 0.5 V, TGRC-MOSFET work function for (ΦITO) is 4.7 eV, CRC-MOSFET work function (ΦM) is 4.2 eV. Mishra et al.[
Figure 18.(Color online) Proposed 6-T SRAM cell using junctionless SOI transistor with the connection.
The dimensions of the structure is gate length 18 nm, Tox 1 nm, Tsi channel thickness 10 nm, substrate thickness 10 nm, doping density in substrate regions 1 × 1018 cm–3, doping density channel 1 × 1018 cm–3, work function of gate material 4.9 eV.
Roy et al.[
Figure 19.(Color online) Structure of n-type junctionless double gate MOSFET.
Saramekala et al.[
Figure 20.(Color online) Dual metal gate (DMG) with recessed source and drain UTB SOI MOSFET.
Work-function of control gate (ΦM1) is 4.8 eV (gold), work-function of screen gate (ΦM2) is 4.6 eV (molybdenum), doping of the channel (Na) is 1015 cm–3, doping of source and drain (Nd) is 1020 cm–3, doping of substrate (Nsub) is 1015 cm–3, oxide thickness of channel (tox) is 1.5–4 nm, thickness of buried (tbox) is 100–300 nm, thickness of recessed is (trsd) 30–100 nm, length of recessed (dbox) is 3 nm, length of the channel (L) is 30–300 nm.
4. Performance comparison and discussion
The performance comparison of different double gate MOSFET has been shown in Table 1 for sub 20 nm technology node including their applications. Since multiple gate MOSFETs have more control of gate over the channel, therefore different DG MOSFET have been considered for performance comparison. Metal gates with high work function are suitable for low OFF-state leakage. The underlap asymmetrical gate increases fringing electric field and leads to better ON-state transistor performance. The absence of depletion region between source/channel and drain in junction-less transistor, improves transistor current drive capability by increasing ON-state current. The high-K dielectric material is preferred as oxide region under gate to improve subthreshold performance parameters and improved switching behavior of transistor. The comparison 20 nm junctionless double gate (JLDG) MOSFET[
5. Conclusion
Various structures of MOSFET have been explored with their structural details and dimensions including applications. Modification in the structure of MOSFET has been done mainly to reduce the short channel effects that include DIBL and SS values. The main motive of these structures is to increase the ON-state current and reduce the OFF-state current. The MOSFET structures are also analyzed for suitable analog/RF performance parameters to obtain a desired range of transconductance, transistor gain, stability factor and critical frequencies. The comparisons between different structures are done on the basis of subthreshold and analog/RF performance parameters. As per comparison made, the junctionless double gate (JLDG) MOSFET provides the lowest subthreshold slope and maximum ION/IOFF ratio for channel length 20 nm. The lowest DIBL obtained from graded channel dual material gate junctionless with channel length 15 nm. Gate engineered transistors of high work function metal contact with various high-K dielectric regions are found suitable to obtain improved subthreshold performance. This shows that gate-engineered multi-gate juntionless MOSFET has good potential to meet future scaling trends with increased compatibility in CMOS technology for any digital/analog and portable IoT or biomedical applications.
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