Lixia Zheng, Yongqi Han, Chenggong Wan, Mouzhao Zhou, Xuyan Li, Jin Wu, Weifeng Sun. Low-power and high-precision SPAD array readout circuit based on built-in clock[J]. Infrared and Laser Engineering, 2023, 52(9): 20220896
- Infrared and Laser Engineering
- Vol. 52, Issue 9, 20220896 (2023)
Fig. 1. Single pixel architecture
Fig. 2. ROIC system structure
Fig. 3. TDC clock signal timing. (a) Gated trigger; (b) Event-driven
Fig. 4. High-precision two-stage TDC circuit
Fig. 5. Four-level GRO structure
Fig. 6. Improved pseudo-differential delay unit
Fig. 7. (a) CP-PLL 32 divides the output waveform; (b) GRO built-in clock function test; (c) PLL control voltage drive GRO built-in clock divide-by-16 waveform graph; (d) Divide-by-16 waveform of the GRO clock for input DC voltage
Fig. 8. (a) TDC overall input-output curve; (b) TDC local input-output curve
Fig. 9. (a) DNL curve; (b) INL curve
Fig. 10. TDC array uniformity
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Table 1. Performance comparison between the circuit in this paper and domestic and foreign design
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