• Journal of Semiconductors
  • Vol. 41, Issue 11, 111401 (2020)
Wei Deng1,2, Haikun Jia1,2, and Baoyong Chi1
Author Affiliations
  • 1Institute of Microelectronics, Tsinghua University, Beijing 100084, China
  • 2Research Institute of Tsinghua University in Shenzhen, Shenzhen 518057, China
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    DOI: 10.1088/1674-4926/41/11/111401 Cite this Article
    Wei Deng, Haikun Jia, Baoyong Chi. Silicon-based FMCW signal generators: A review[J]. Journal of Semiconductors, 2020, 41(11): 111401 Copy Citation Text show less
    Block diagram of the FMCW transceiver.
    Fig. 1. Block diagram of the FMCW transceiver.
    (Color online) FMCW principle of a sawtooth wave.
    Fig. 2. (Color online) FMCW principle of a sawtooth wave.
    FMCW PLL using direct-modulating VCO.
    Fig. 3. FMCW PLL using direct-modulating VCO.
    Block diagram of DDFS-based FMCW generator.
    Fig. 4. Block diagram of DDFS-based FMCW generator.
    Block diagram of the FMCW PLL using feedback modulation.
    Fig. 5. Block diagram of the FMCW PLL using feedback modulation.
    (Color online) Block diagram of the FMCW PLL using digital modulation.
    Fig. 6. (Color online) Block diagram of the FMCW PLL using digital modulation.
    Block diagram of the digital PLL based FMCW signal generator using TPM.
    Fig. 7. Block diagram of the digital PLL based FMCW signal generator using TPM.
    Simplified linear model of the digital PLL based FMCW signal generator.
    Fig. 8. Simplified linear model of the digital PLL based FMCW signal generator.
    (Color online) Block diagram of SSPLL based FMCW signal generator.
    Fig. 9. (Color online) Block diagram of SSPLL based FMCW signal generator.
    Block diagram of phase domain digital PLL based FMCW signal generator.
    Fig. 10. Block diagram of phase domain digital PLL based FMCW signal generator.
    (Color online) Block diagram of the TPM digital PLL with gain mismatch.
    Fig. 11. (Color online) Block diagram of the TPM digital PLL with gain mismatch.
    Block diagram of the FMCW signal generator using a type-III frequency ramp estimator.
    Fig. 12. Block diagram of the FMCW signal generator using a type-III frequency ramp estimator.
    The concept of DCO pre-distortion scheme.
    Fig. 13. The concept of DCO pre-distortion scheme.
    Block diagram of the TPM digital PLL with digital pre-distortion.
    Fig. 14. Block diagram of the TPM digital PLL with digital pre-distortion.
    Adaptive piecewise-linear DPD in Ref. [40].
    Fig. 15. Adaptive piecewise-linear DPD in Ref. [40].
    Adaptive piecewise-linear DPD in Ref. [28].
    Fig. 16. Adaptive piecewise-linear DPD in Ref. [28].
    Ref.TopologyRef. Freq. (MHz)Freq. (GHz)BW/Tchirp(GHz/μs) Rms FMerr(kHz) Max slope (GHz/μs) Norm. slope (GHz/μs) Phase noise1(dBc/Hz) WaveformPower (mW)Tech.
    1Normalized to 79 GHz. 2A clean-up PLL is required to generate the 1 GHz reference clock for FMCW synthesizer.
    [28] TPM52220.2/1.28000.160.66−97Sawtooth triangular2065 nm CMOS
    [29] TPM80161.5/102300.150.75−92.4Sawtooth triangular4428 nm CMOS
    [2] TPM10002201/406000.0250.1−94Sawtooth triangular>12040 nm CMOS
    [35] TPM276.890.95/8019000.0190.17−86.2Triangular14.865 nm CMOS
    [34] TPM40601/2103840.470.06−88Triangular4865 nm CMOS
    [41] Frac-N125201.25/508000.0250.1−97Sawtooth triangular240130 nm SiGe
    Table 1. Performance summary of the state-of-the-art work.