Author Affiliations
1 Device Reliability Assurance Department, No.808 Institute of the Eighth Academy of China Aerospace Science and Technology Corporation, Shanghai 201109, China2 Radiation Effect Laboratory, Xinjiang Technical Institute of Physics and Chemistry, Chinese Academy of Sciences, Urumqi, Xinjiang 830011, Chinashow less
Fig. 1. Block diagram of CMV4000 image sensor
Fig. 2. Cross-sectional diagram of 8T pixel unit
Fig. 3. SEU diagram of standard 6T structure SRAM storage unit after exposure to heavy-ion irradiation[13]
Fig. 4. Block diagram of 8T-global exposure CIS single-particle online detection system
Fig. 5. Abnormal images after SEU in offset register. (a) Nth; (b) (N+1)th; (c) (N+2)th
Fig. 6. Three-dimensional stereograms of image abnormal mode after SEU in offset register. (a) Nth; (b) (N+1)th; (c) (N+2)th
Fig. 7. Image abnormal mode after SEU in LVDS output register
Fig. 8. Image abnormal mode after SEU in row-decoder address decoder
Fig. 9. Image abnormal mode after SEU in output clock register
Fig. 10. Working diagram of 8-channel LVDS. (a) Reading out line by line for LVDS; (b) pixel output line coordinate corresponding to each LVDS
Fig. 11. Timing diagram of 10-bit pixel output
Fig. 12. Schematic of corrupted code for 10-bit pixel output
Ion specie | Incident angle | Range /μm | LET /(MeV·cm2·mg-1) | Experimental environment |
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16O | Vertical | 95.2 | 3.1 | Vacuum tank | 27Si | Vertical | 50.7 | 9.3 | Vacuum tank | 35Cl | Vertical | 42.8 | 13.4 | Vacuum tank | 48Ti | Vertical | 32.9 | 22.2 | Vacuum tank | 74Ge | Vertical | 29.95 | 37.37 | Vacuum tank |
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Table 1. Ion information for heavy-ion irradiation tests
Ion specie | LET /(MeV·cm2·mg-1) | Flux /(ion·cm-2·s-1) | Fluence /(106 ion·cm-2) | Number of SEU | σ /(cm2·device-1) |
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16O | 3.1 | 2000 | 1.5 | 0 | 0 | 27Si | 9.3 | 2000 | 1.3 | 377 | 2.9×10-4 | 35Cl | 13.4 | 2000 | 3.6 | 3849 | 1.07×10-3 | 48Ti | 22.2 | 2000 | 0.76 | 8074 | 1.06×10-2 | 74Ge | 37.37 | 2000 | 1 | 13062 | 1.3×10-2 |
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Table 2. CIS SEU test data
Register name | Functional description | Abnormal image representation | LET /(MeV·cm2·mg-1) |
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Offset register | For pixel dark signal correction | Output image of "always zero" | 9.3 | LVDS register | Control pixel output channel | LVDS output channel severaladjacent column output exception | 13.4,22.2,37.37 | Row-decoder register | Row address addressing, controllingline pixel exposure and readout | Some zero row outputs | 13.4,22.2,37.37 | Output clock register | Ensuring alignment with deviceclock and 10-bit pixel codevalue output in turn | Whole image messy code | 22.2,37.37 |
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Table 3. Image abnormal modes caused by SEU
Register name | Register address | Default of gray value | Register function description |
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Offset register | 100-101 | 16323 | Value in this register defining dark signal correction appliedto pixel output signal (minimum is 0, maximum is 16383) |
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Table 4. Original setting of CMV4000 offset register