[1] H L Liu, A Shirane, K Okada et al. A 265-
[2]
[3]
[4] T A D Riley, M A Copeland, T A Kwasniewski. Delta-sigma modulation in fractional-N frequency synthesis. IEEE J Solid-State Circuits, 28, 553(1993).
[5]
[6] M H Perrott, M D Trott, C G Sodini. A modeling approach for Σ-Δ fractional-N frequency synthesizers allowing straightforward noise analysis. IEEE J Solid-State Circuits, 37, 1028(2002).
[7] C R Ho, M S W Chen. Smoothing the way for digital phase-locked loops: Clock generation in the future with digital signal processing for mitigating spur and interference. IEEE Microw, 20, 80(2019).
[8] H Hedayati, W Khalil, B Bakkaloglu. A 1 MHz bandwidth, 6 GHz 0.18
[9] T H Lin, C L Ti, Y H Liu. Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs. IEEE Trans Circuits Syst I, 56, 877(2009).
[10] V S Sadeghi, H Miar Naimi, M P Kennedy. The role of charge pump mismatch in the generation of integer boundary spurs in fractional-N frequency synthesizers: Why worse can be better. IEEE Trans Circuits Syst II, 60, 862(2013).
[11] E Temporiti, G Albasini, I Bietti et al. A 700-kHz bandwidth ΔΣ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications. IEEE J Solid-State Circuits, 39, 1446(2004).
[12] H Arora, N Klemmer, J C Morizio et al. Enhanced phase noise modeling of fractional-N frequency synthesizers. IEEE Trans Circuits Syst I, 52, 379(2005).
[13]
[14] J S Lee, M S Keel, S I Lim et al. Charge pump with perfect current matching characteristics in phase-locked loops. Electron Lett, 36, 1907(2000).
[15] I C Hwang, D Baek. A 0.93-mA spur-enhanced frequency synthesizer for L1/L5 dual-band GPS/Galileo RF receiver. IEEE Microw Wirel Compon Lett, 20, 355(2010).
[16] A Mazzanti, M B Vahidfar, M Sosio et al. A low phase-noise multi-phase LO generator for wideband demodulators based on reconfigurable sub-harmonic mixers. IEEE J Solid-State Circuits, 45, 2104(2010).
[17] W H Chen, W F Loke, B Jung. A 0.5-V, 440-
[18] W F Lou, P Feng, H Y Wang et al. Low power fast settling multi-standard current reusing CMOS fractional-N frequency synthesizer. J Semicond, 33, 045004(2012).
[19] Y C Choi, Y J Seong, Y J Yoo et al. Multi-standard hybrid PLL with low phase-noise characteristics for GSM/EDGE and LTE applications. IEEE Trans Microw Theory Tech, 63, 3254(2015).
[20] C M Lai, K W Tan, Y J Chen et al. A UWB impulse-radio timed-array radar with time-shifted direct-sampling architecture in 0.18-
[21] P Larsson. A 2-1600-MHz CMOS clock recovery PLL with low-Vdd capability. IEEE J Solid-State Circuits, 34, 1951(1999).
[22]
[23] A Lahiri, N Gupta, A Kumar et al. A 600
[24]
[25] S Cheng, H Tong, J Silva-Martinez et al. Design and analysis of an ultrahigh-speed glitch-free fully differential charge pump with minimum output current variation and accurate matching. IEEE Trans Circuits Syst II, 53, 843(2006).
[26] Y C Yang, S S Lu. A single-VCO fractional-N frequency synthesizer for digital TV tuners. IEEE Trans Ind Electron, 57, 3207(2010).
[27] M Abdulaziz, T Forsberg, M Tormanen et al. A 10-mW mm-wave phase-locked loop with improved lock time in 28-nm FD-SOI CMOS. IEEE Trans Microw Theory Tech, 67, 1588(2019).
[28] C F Liang, S H Chen, S I Liu. A digital calibration technique for charge pumps in phase-locked systems. IEEE J Solid-State Circuits, 43, 390(2008).
[29] W H Chiu, T S Chang, T H Lin. A charge pump current mismatch calibration technique for ΔΣ fractional-N PLLs in 0.18-
[30] Y W Chen, Y H Yu, Y J E Chen. A 0.18-
[31] S B Liu, D P Sun, R X Ding et al. A multiplexing DAPD technique for fast-locking and charge pumps calibration in PLLs. IEEE Microw Wirel Compon Lett, 29, 535(2019).
[32] Z Zhang, L Y Liu, N J Wu et al. Source-switched charge pump with reverse leakage compensation technique for spur reduction of wideband PLL. Electron Lett, 52, 1211(2016).
[33] K Y Shen, S F Syed Farooq, Y P Fan et al. A flexible, low-power analog PLL for SoC and processors in 14nm CMOS. IEEE Trans Circuits Syst I, 65, 2109(2018).
[34]
[35] S Shekhar, D Gangopadhyay, E C Woo et al. A 2.4-GHz extended-range type-I ΔΣ fractional-N synthesizer with 1.8-MHz loop bandwidth and −110-dBc/Hz phase noise. IEEE Trans Circuits Syst II, 58, 472(2011).
[36] L Lu, J H Chen, L Yuan et al. An 18-mW 1.175–2-GHz frequency synthesizer with constant bandwidth for DVB-T tuners. IEEE Trans Microw Theory Tech, 57, 928(2009).
[37] W F Lou, X D Liu, P Feng et al. An integrated 0.38–6 GHz, 9–12 GHz fully differential fractional-N frequency synthesizer for multi-standard reconfigurable MIMO communication application. Analog Integr Circ Sig Process, 78, 807(2014).
[38] Z Zhang, J C Yang, L Y Liu et al. 0.1–5 GHz wideband ΔΣ fractional-N frequency synthesiser for software-defined radio application. IET Circuits Devices Syst, 13, 1071(2019).
[39] Z Zhang, L Y Liu, P Feng et al. A 2.4–3.6-GHz wideband subharmonically injection-locked PLL with adaptive injection timing alignment technique. IEEE Trans VLSI Syst, 25, 929(2017).
[40] M M Elsayed, M Abdul-Latif, E Sanchez-Sinencio. A spur-frequency-boosting PLL with a –74 dBc reference-spur suppression in 90 nm digital CMOS. IEEE J Solid-State Circuits, 48, 2104(2013).
[41]
[42]
[43] A Lahiri, N Gupta. A 0.0175mm2 600
[44] B Sadhu, M A Ferriss, A S Natarajan et al. A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing. IEEE J Solid-State Circuits, 48, 1138(2013).
[45] M Ferriss, J O Plouchart, A Natarajan et al. An integral path self-calibration scheme for a dual-loop PLL. IEEE J Solid-State Circuits, 48, 996(2013).
[46]
[47] Y F Sun, Z Zhang, N Xu et al. A 1.75 mW 1.1 GHz semi-digital fractional-N PLL with TDC-less hybrid loop control. IEEE Microw Wirel Compon Lett, 22, 654(2012).
[48] M Ferriss, A Rylyakov, J A Tierno et al. A 28 GHz Hybrid PLL in 32 nm SOI CMOS. IEEE J Solid-State Circuits, 49, 1027(2014).
[49] M Ferriss, B Sadhu, A Rylyakov et al. A 13.1-to-28GHz fractional-N PLL in 32nm SOI CMOS with a ΔΣ noise-cancellation scheme. IEEE International Solid-State Circuit Conference, 192(2015).
[50] W J Yin, R Inti, A Elshazly et al. A 0.7-to-3.5 GHz 0.6-to-2.8 mW highly digital phase-locked loop with bandwidth tracking. IEEE J Solid-State Circuits, 46, 1870(2011).
[51] D Kim, S Cho. A hybrid PLL using low-power GRO-TDC for reduced in-band phase noise. IEEE Trans Circuits Syst II, 66, 232(2019).
[52] J H Zhu, R K Nandwana, G H Shu et al. A 0.0021 mm2 1.82 mW 2.2 GHz PLL using time-based integral control in 65 nm CMOS. IEEE J Solid-State Circuits, 52, 8(2017).
[53]
[54] A Homayoun, B Razavi. Analysis of phase noise in phase/frequency detectors. IEEE Trans Circuits Syst I, 60, 529(2013).
[55]
[56] J Jin, X M Liu, T T Mo et al. Quantization noise suppression in fractional-N PLLs utilizing glitch-free phase switching multi-modulus frequency divider. IEEE Trans Circuits Syst I, 59, 926(2012).
[57] S Levantino, G Marzin, C Samori et al. A wideband fractional-N PLL with suppressed charge-pump noise and automatic loop filter calibration. IEEE J Solid-State Circuits, 48, 2419(2013).
[58] L Kong, B Razavi. A 2.4 GHz 4 mW integer-N inductorless RF synthesizer. IEEE J Solid-State Circuits, 51, 626(2016).
[59] S Levantino, L Romano, S Pellerano et al. Phase noise in digital frequency dividers. IEEE J Solid-State Circuits, 39, 775(2004).
[60] D Tasca, M Zanuso, S Levantino et al. Low-power divider retiming in a 3–4 GHz fractional-N PLL. IEEE Trans Circuits Syst II, 58, 200(2011).
[61]
[62] Z Zhang, J C Yang, L Y Liu et al. A 0.9–2.25-GHz sub-0.2-mW/GHz compact low-voltage low-power hybrid digital PLL with loop bandwidth-tracking technique. IEEE Trans VLSI Syst, 26, 933(2018).
[63] J Lee, S Park, S Cho. A 470-
[64] L Wu, H C Luong. Analysis and design of a 0.6 V 2.2 mW 58.5-to-72.9 GHz divide-by-4 injection-locked frequency divider with harmonic boosting. IEEE Trans Circuits Syst I, 60, 2001(2013).
[65] S L Jang, W C Lai, G Y Lin et al. Injection-locked frequency divider with a resistively distributed resonator for wide-locking-range performance. IEEE Trans Microw Theory Tech, 67, 505(2019).
[66] Y L Yeh, H Y Chang. Design and analysis of a W-band divide-by-three injection-locked frequency divider using second harmonic enhancement technique. IEEE Trans Microw Theory Tech, 60, 1617(2012).
[67] A Ghilioni, A Mazzanti, F Svelto. Analysis and design of mm-wave frequency dividers based on dynamic latches with load modulation. IEEE J Solid-State Circuits, 48, 1842(2013).
[68] A I Hussein, J Paramesh. Design and self-calibration techniques for inductor-less millimeter-wave frequency dividers. IEEE J Solid-State Circuits, 52, 1521(2017).
[69] Y Chen, Z S Yang, X T Zhao et al. A 6.5 × 7
[70]
[71]
[72]
[73]
[74] J W Moon, K C Choi, W Y Choi. A 0.4-V, 90~350-MHz PLL with an active loop-filter charge pump. IEEE Trans Circuits Syst II, 61, 319(2014).
[75] K H Cheng, Y C Tsai, Y L Lo et al. A 0.5-V 0.4–2.24-GHz inductorless phase-locked loop in a system-on-chip. IEEE Trans Circuits Syst I, 58, 849(2011).
[76] Y L Lo, W B Yang, T S Chao et al. Designing an ultralow-voltage phase-locked loop using a bulk-driven technique. IEEE Trans Circuits Syst II, 56, 339(2009).
[77]
[78]
[79] S Ikeda, S Y Lee, H Ito et al. A 0.5 V 5.96-GHz PLL with amplitude-regulated current-reuse VCO. IEEE Microw Wirel Compon Lett, 27, 302(2017).
[80] G R Gangasani, P R Kinget. A 0.5 V, 9-GHz sub-integer frequency synthesizer using multi-phase injection-locked prescaler for phase-switching-based programmable division with automatic injection-lock calibration in 45-nm CMOS. IEEE Trans Circuits Syst II, 66, 803(2019).
[81] E Hegazi, A A Abidi. Varactor characteristics, oscillator tuning curves, and AM-FM conversion. IEEE J Solid-State Circuits, 38, 1033(2003).
[82] T H Lin, W J Kaiser. A 900-MHz 2.5-mA CMOS frequency synthesizer with an automatic SC tuning loop. IEEE J Solid-State Circuits, 36, 424(2001).
[83] A Aktas, M Ismail. CMOS PLL calibration techniques. IEEE Circuits Devices Mag, 20, 6(2004).
[84] T H Lin, Y J Lai. An agile VCO frequency calibration technique for a 10-GHz CMOS PLL. IEEE J Solid-State Circuits, 42, 340(2007).
[85]
[86] D P Huang, W Li, J Zhou et al. A frequency synthesizer with optimally coupled QVCO and harmonic-rejection SSBmixer for multi-standard wireless receiver. IEEE J Solid-State Circuits, 46, 1307(2011).
[87] J Shin, H Shin. A fast and high-precision VCO frequency calibration technique for wideband ΔΣ fractional-N frequency synthesizers. IEEE Trans Circuits Syst I, 57, 1573(2010).
[88] J Shin, H Shin. A 1.9–3.8 GHz ΔΣ fractional-N PLL frequency synthesizer with fast auto-calibration of loop bandwidth and VCO frequency. IEEE J Solid-State Circuits, 47, 665(2012).
[89]
[90]
[91]
[92] C Y Li, C L Lee, M H Hu et al. A fast locking-in and low jitter PLLWith a process-immune locking-in monitor. IEEE Trans Very Large Scale Integr VLSI Syst, 22, 2216(2014).
[93] B Zhao, Y Lian, H Z Yang. A low-power fast-settling bond-wire frequency synthesizer with a dynamic-bandwidth scheme. IEEE Trans Circuits Syst I, 60, 1188(2013).
[94]
[95]
[96] X D Liu, P Feng, L Y Liu et al. Low power low phase noise phase locked loop frequency synthesizer with fast locking mode for 2.4 GHz applications. Jpn J Appl Phys, 53, 04EE18(2014).
[97] W H Chiu, Y H Huang, T H Lin. A dynamic phase error compensation technique for fast-locking phase-locked loops. IEEE J Solid-State Circuits, 45, 1137(2010).
[98]
[99]
[100] G Zhang. Linearised charge pump independent of current mismatch through timing rearrangement. Electron Lett, 46, 33(2010).
[101]
[102] D W Jee, Y Suh, B Kim et al. A FIR-embedded phase interpolator based noise filtering for wide-bandwidth fractional-N PLL. IEEE J Solid-State Circuits, 48, 2795(2013).
[103]
[104] C H Heng, B S Song. A 1.8-GHz CMOS fractional-N frequency synthesizer with randomized multiphase VCO. IEEE J Solid-State Circuits, 38, 848(2003).
[105] C C Hung, S I Liu. A noise filtering technique for fractional-N frequency synthesizers. IEEE Trans Circuits Syst II, 58, 139(2011).
[106] P Park, D Park, S Cho. A 2.4 GHz fractional-N frequency synthesizer with high-OSR ΔΣ modulator and nested PLL. IEEE J Solid-State Circuits, 47, 2433(2012).
[107]
[108] D Park, S Cho. A 14.2 mW 2.55-to-3 GHz cascaded PLL with reference injection and 800 MHz delta-sigma modulator in 0.13
[109] R K Nandwana, T Anand, S Saxena et al. A calibration-free fractional-N ring PLL using hybrid phase/current-mode phase interpolation method. IEEE J Solid-State Circuits, 50, 882(2015).
[110] M Gupta, B S Song. A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration. IEEE J Solid-State Circuits, 41, 2842(2006).
[111] A Swaminathan, K J Wang, I Galton. A wide-bandwidth 2.4 GHz ISM band fractional-N PLL with adaptive phase noise cancellation. IEEE J Solid-State Circuits, 42, 2639(2007).
[112]
[113] S E Meninger, M H Perrott. A 1-MHz bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise. IEEE J Solid-State Circuits, 41, 966(2006).
[114] H Y Jian, Z W Xu, Y C Wu et al. A fractional-N PLL for multiband (0.8–6 GHz) communications using binary-weighted D/A differentiator and offset-frequency Δ-Σ modulator. IEEE J Solid-State Circuits, 45, 768(2010).
[115]
[116] X Y Yu, Y F Sun, W Rhee et al. An FIR-embedded noise filtering method for ΔΣ fractional-N PLL clock generators. IEEE J Solid-State Circuits, 44, 2426(2009).
[117] X Y Yu, Y F Sun, W Rhee et al. A ΔΣ fractional-N synthesizer with customized noise shaping for WCDMA/HSDPA applications. IEEE J Solid-State Circuits, 44, 2193(2009).
[118] L Kong, B Razavi. A 2.4-GHz RF fractional-N synthesizer with BW = 0.25
[119] A Sanyal, N Sun, X Y Yu et al. Fractional-N PLL with multi-element fractional divider for noise reduction. Electron Lett, 52, 809(2016).
[120] Y L Zhang, A Sanyal, X Y Yu et al. A fractional-N PLL with space–time averaging for quantization noise reduction. IEEE J Solid-State Circuits, 55, 602(2020).
[121]
[122]
[123] J Lee, H D Wang. Study of subharmonically injection-locked PLLs. IEEE J Solid-State Circuits, 44, 1539(2009).
[124] Z Zhang, J C Yang, L Y Liu et al. An 18–23 GHz 57.4-fs RMS jitter −253.5-dB FoM sub-harmonically injection-locked all-digital PLL with single-ended injection technique and ILFD aided adaptive injection timing alignment technique. IEEE Trans Circuits Syst I, 66, 3733(2019).
[125] Y C Huang, S I Liu. A 2.4-GHz subharmonically injection-locked PLL with self-calibrated injection timing. IEEE J Solid-State Circuits, 48, 417(2013).
[126] C L Wei, T K Kuan, S I Liu. A subharmonically injection-locked PLL with calibrated injection pulsewidth. IEEE Trans Circuits Syst II, 62, 548(2015).
[127]
[128]
[129]
[130] S Choi, S Yoo, Y Lim et al. A PVT-robust and low-jitter ring-VCO-based injection-locked clock multiplier with a continuous frequency-tracking loop using a replica-delay cell and a dual-edge phase detector. IEEE J Solid-State Circuits, 51, 1878(2016).
[131] M Kim, S Choi, T Seong et al. A low-jitter and fractional-resolution injection-locked clock multiplier using a DLL-based real-time PVT calibrator with replica-delay cells. IEEE J Solid-State Circuits, 51, 401(2016).
[132] D Lee, T Lee, Y J Kim et al. A 21%-jitter-improved self-aligned dividerless injection-locked PLL with a VCO control voltage ripple-compensated phase detector. IEEE Trans Circuits Syst II, 63, 733(2016).
[133] H Y Chang, Y L Yeh, Y C Liu et al. A low-jitter low-phase-noise 10-GHz sub-harmonically injection-locked PLL with self-aligned DLL in 65-nm CMOS technology. IEEE Trans Microw Theory Tech, 62, 543(2014).
[134] H Y Chang, C C Chan, I Y E Shen et al. Design and analysis of CMOS low-phase-noise low-jitter subharmonically injection-locked VCO with FLL self-alignment technique. IEEE Trans Microw Theory Tech, 64, 4632(2016).
[135] K Huang, Z Q Wang, X Q Zheng et al. A 80 mW 40 Gb/s transmitter with automatic serializing time window search and 2-tap pre-emphasis in 65 nm CMOS technology. IEEE Trans Circuits Syst I, 62, 1441(2015).
[136] S Yoo, S Choi, J Kim et al. A low-integrated-phase-noise 27–30-GHz injection-locked frequency multiplier with an ultra-low-power frequency-tracking loop for mm-wave-band 5G transceivers. IEEE J Solid-State Circuits, 53, 375(2018).
[137] H Yoon, S Park, J Choi. A low-jitter injection-locked multi-frequency generator using digitally controlled oscillators and time-interleaved calibration. IEEE J Solid-State Circuits, 54, 1564(2019).
[138]
[139] S Choi, S Yoo, Y Lee et al. An ultra-low-jitter 22.8-GHz ring-LC-hybrid injection-locked clock multiplier with a multiplication factor of 114. IEEE J Solid-State Circuits, 54, 927(2019).
[140] D Shin, K J Koh. An injection frequency-locked loop: Autonomous injection frequency tracking loop with phase noise self-calibration for power-efficient mm-wave signal sources. IEEE J Solid-State Circuits, 53, 825(2018).
[141]
[142] X L Liu, H C Luong. A fully integrated 0.27-THz injection-locked frequency synthesizer with frequency-tracking loop in 65-nm CMOS. IEEE J Solid-State Circuits, 55, 1051(2020).
[143] Y H Tseng, C W Yeh, S I Liu. A 2.25–2.7 GHz area-efficient subharmonically injection-locked fractional-N frequency synthesizer with a fast-converging correlation loop. IEEE Trans Circuits Syst I, 64, 811(2017).
[144] J C Yang, Z Zhang, N Qi et al. 2.4–3.2 GHz robust self-injecting injection-locked phase-locked loop. Jpn J Appl Phys, 57, 04FF05(2018).
[145]
[146] J C Yang, Z Zhang, N Qi et al. A 0.45-to-1.8 GHz synthesized injection-locked bang-bang phase locked loop with fine frequency tuning circuits. Sci China Inf Sci, 62, 62405(2019).
[147]
[148] X Gao, E A M Klumperink, M Bohsali et al. A low noise sub-sampling PLL in which divider noise is eliminated and PD/CP noise is not multiplied by N2. IEEE J Solid-State Circuits, 44, 3253(2009).
[149] X Gao, E A M Klumperink, G Socci et al. Spur reduction techniques for phase-locked loops exploiting A sub-sampling phase detector. IEEE J Solid-State Circuits, 45, 1809(2010).
[150]
[151] V Szortyka, Q X Shi, K Raczkowski et al. A 42 mW 200 fs-jitter 60 GHz sub-sampling PLL in 40 nm CMOS. IEEE J Solid-State Circuits, 50, 2025(2015).
[152] A Sharkia, S Mirabbasi, S Shekhar. A type-I sub-sampling PLL with a 100 × 100 μm2 footprint and –255-dB FOM. IEEE J Solid-State Circuits, 53, 3553(2018).
[153]
[154] C W Hsu, K Tripurari, S A Yu et al. A sub-sampling-assisted phase-frequency detector for low-noise PLLs with robust operation under supply interference. IEEE Trans Circuits Syst I, 62, 90(2015).
[155] D G Lee, P P Mercier. A sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of –256 dB. IEEE J Solid-State Circuits, 1(2019).
[156]
[157]
[158] T Siriburanon, S Kondo, M Katsuragi et al. A low-power low-noise mm-wave subsampling PLL using dual-step-mixing ILFD and tail-coupling quadrature injection-locked oscillator for IEEE 802.11ad. IEEE J Solid-State Circuits, 51, 1246(2016).
[159]
[160]
[161]
[162] W El-Halwagy, A Nag, P Hisayasu et al. A 28-GHz quadrature fractional-N frequency synthesizer for 5G transceivers with less than 100-fs jitter based on cascaded PLL architecture. IEEE Trans Microw Theory Tech, 65, 396(2017).
[163]
[164] S S Nagam, P R Kinget. A low-jitter ring-oscillator phase-locked loop using feedforward noise cancellation with a sub-sampling phase detector. IEEE J Solid-State Circuits, 53, 703(2018).
[165] J Kim, Y Lim, H Yoon et al. An ultra-low-jitter, mmW-band frequency synthesizer based on digital subsampling PLL using optimally spaced voltage comparators. IEEE J Solid-State Circuits, 54, 3466(2019).
[166]
[167]
[168] Z Zhang, G Zhu, C P Yue. A 0.65-V 12-16-GHz sub-sampling PLL with 56.4-fsrms integrated jitter and –256.4-dB FoM. IEEE J Solid-State Circuits, 55, 1665(2020).
[169]
[170] D Y Liao, F F Dai, B Nauta et al. A 2.4-GHz 16-phase sub-sampling fractional-N PLL with robust soft loop switching. IEEE J Solid-State Circuits, 53, 715(2018).
[171]
[172] W S Chang, P C Huang, T C Lee. A fractional-N divider-less phase-locked loop with a subsampling phase detector. IEEE J Solid-State Circuits, 49, 2964(2014).
[173]
[174] A T Narayanan, M Katsuragi, K Kimura et al. A fractional-N sub-sampling PLL using a pipelined phase-interpolator with an FoM of –250 dB. IEEE J Solid-State Circuits, 51, 1630(2016).
[175] K Raczkowski, N Markulic, B Hershberg et al. A 9.2–12.7 GHz wideband fractional-N subsampling PLL in 28 nm CMOS with 280 fs RMS jitter. IEEE J Solid-State Circuits, 50, 1203(2015).
[176] N Markulic, K Raczkowski, E Martens et al. A DTC-based subsampling PLL capable of self-calibrated fractional synthesis and two-point modulation. IEEE J Solid-State Circuits, 51, 3078(2016).
[177] N Markulic, P T Renukaswamy, E Martens et al. A 5.5-GHz background-calibrated subsampling polar transmitter with –41.3-dB EVM at 1024 QAM in 28-nm CMOS. IEEE J Solid-State Circuits, 54, 1059(2019).
[178] Q X Shi, K Bunsen, N Markulic et al. A self-calibrated 16-GHz subsampling-PLL-based fast-chirp FMCW modulator with 1.5-GHz bandwidth. IEEE J Solid-State Circuits, 54, 3503(2019).
[179]
[180] T Siriburanon, S Kondo, K Kimura et al. A 2.2 GHz –242 dB-FOM 4.2 mW ADC-PLL using digital sub-sampling architecture. IEEE J Solid-State Circuits, 51, 1385(2016).
[181]
[182] W S Chang, T C Lee. A 5 GHz fractional-N ADC-based digital phase-locked loops with –243.8 dB FOM. IEEE Trans Circuits Syst I, 63, 1845(2016).
[183] M L Liu, R Ma, S B Liu et al. A 5-GHz low-power low-noise integer-N digital subsampling PLL with SAR ADC PD. IEEE Trans Microw Theory Tech, 66, 4078(2018).
[184] D Y Liao, Y C Zhang, F F Dai et al. An mm-wave synthesizer with robust locking reference-sampling PLL and wide-range injection-locked VCO. IEEE J Solid-State Circuits, 55, 536(2020).
[185]
[186] C T Ko, T K Kuan, R P Shen et al. A 7-nm FinFET CMOS PLL with 388-fs jitter and –80-dBc reference spur featuring a track-and-hold charge pump and automatic loop gain control. IEEE J Solid-State Circuits, 55, 1043(2020).
[187] J Sharma, H Krishnaswamy. A 2.4-GHz reference-sampling phase-locked loop that simultaneously achieves low-noise and low-spur performance. IEEE J Solid-State Circuits, 54, 1407(2019).
[188]
[189]
[190] W H Wu, C W Yao, K Godbole et al. A 28-nm 75-fsrms analog fractional-N sampling PLL with a highly linear DTC incorporating background DTC gain calibration and reference clock duty cycle correction. IEEE J Solid-State Circuits, 54, 1254(2019).
[191]
[192] J C Tao, C H Heng. A 2.2-GHz 3.2-mW DTC-free sampling ΔΣ fractional-N PLL with –110-dBc/Hz in-band phase noise and –246-dB FoM and –83-dBc reference spur. IEEE Trans Circuits Syst I, 66, 3317(2019).