• Journal of Semiconductors
  • Vol. 41, Issue 11, 111402 (2020)
Zhao Zhang1,2
Author Affiliations
  • 1State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China
  • 2Graduate School of Advanced Science and Engineering, Hiroshima University, 1-3-1 Kagamiyama, Higashi-Hiroshima, 739-8530, Japan
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    DOI: 10.1088/1674-4926/41/11/111402 Cite this Article
    Zhao Zhang. CMOS analog and mixed-signal phase-locked loops: An overview[J]. Journal of Semiconductors, 2020, 41(11): 111402 Copy Citation Text show less
    (a). Block diagram of the basic CPPLL. (b) Transfer curve of PFD and CP. (c) Timing diagram.
    Fig. 1. (a). Block diagram of the basic CPPLL. (b) Transfer curve of PFD and CP. (c) Timing diagram.
    Linear phase noise model, CPPLL loop dynamics, and noise transfer functions of each building blocks.
    Fig. 2. Linear phase noise model, CPPLL loop dynamics, and noise transfer functions of each building blocks.
    (Color online) (a) Timing diagram of the CPPLL with CP current mismatch. (b) VC-ripple-induced reference spur on the PLL output spectrum. (c) VC-ripple-induced deterministic jitter (DJ) on the PLL output clock eye.
    Fig. 3. (Color online) (a) Timing diagram of the CPPLL with CP current mismatch. (b) VC-ripple-induced reference spur on the PLL output spectrum. (c) VC-ripple-induced deterministic jitter (DJ) on the PLL output clock eye.
    (Color online) Quantization noise effect with (a) narrow and (b) wide loop bandwidth, respectively.
    Fig. 4. (Color online) Quantization noise effect with (a) narrow and (b) wide loop bandwidth, respectively.
    (Color online) Degradation of the in-band phase noise and fractional spur due to the PFD/CP nonlinearity.
    Fig. 5. (Color online) Degradation of the in-band phase noise and fractional spur due to the PFD/CP nonlinearity.
    Schematics of CPs with current mismatch suppression techniques.
    Fig. 6. Schematics of CPs with current mismatch suppression techniques.
    Conceptual block diagram of the CPPLL with CP current mismatch calibration technique.
    Fig. 7. Conceptual block diagram of the CPPLL with CP current mismatch calibration technique.
    Examples of (a) SC-LPF[33] and (b) SC-LPF with RC-LPF (sampling loop filter)[3].
    Fig. 8. Examples of (a) SC-LPF[33] and (b) SC-LPF with RC-LPF (sampling loop filter)[3].
    (Color online) Conceptual block diagram of (a) fully differential CPPLL and (b) CPPLL with spur frequency boosting technique.
    Fig. 9. (Color online) Conceptual block diagram of (a) fully differential CPPLL and (b) CPPLL with spur frequency boosting technique.
    (Color online) Area reduction techniques: (a) capacitance multiplier, (b) dual-path loop CPPLL, (c) hybrid digital PLL, and (d) time-based PLL.
    Fig. 10. (Color online) Area reduction techniques: (a) capacitance multiplier, (b) dual-path loop CPPLL, (c) hybrid digital PLL, and (d) time-based PLL.
    (a) Divider with retiming DFF. (b) Divider with retiming DFF and calibration circuit for preventing metastability issue.
    Fig. 11. (a) Divider with retiming DFF. (b) Divider with retiming DFF and calibration circuit for preventing metastability issue.
    (Color online) (a) Gated CP. (b) Gated CP with current mismatch suppression technique. (c) Retiming DFF operates at prescaler output frequency. (d) PLL with current reuse technique.
    Fig. 12. (Color online) (a) Gated CP. (b) Gated CP with current mismatch suppression technique. (c) Retiming DFF operates at prescaler output frequency. (d) PLL with current reuse technique.
    AFC techniques: (a) Vtune monitoring technique, (b) relative period comparison technique, (c) counter-based AFC, (d) VCO-counting AFC, (e) four-phase counting AFC, and (f) TDC-assisted AFC.
    Fig. 13. AFC techniques: (a) Vtune monitoring technique, (b) relative period comparison technique, (c) counter-based AFC, (d) VCO-counting AFC, (e) four-phase counting AFC, and (f) TDC-assisted AFC.
    Fast fine locking techniques: (a) dynamic loop bandwidth switching technique, (b) frequency presetting technique, and (c) dynamic phase error compensation (DPEC) technique.
    Fig. 14. Fast fine locking techniques: (a) dynamic loop bandwidth switching technique, (b) frequency presetting technique, and (c) dynamic phase error compensation (DPEC) technique.
    (Color online) CP linearization techniques: (a) basic idea, (b) CP offset current technique, (c) CP offset current technique with sampling loop filter, and (d) PFD offset delay technique.
    Fig. 15. (Color online) CP linearization techniques: (a) basic idea, (b) CP offset current technique, (c) CP offset current technique with sampling loop filter, and (d) PFD offset delay technique.
    Quantization noise suppression techniques: (a) sub-integer-N divider technique, (b) phase-interpolator (PI) based compensation technique, (c) DTC-based compensation technique, (d) phase-domain quantization noise filtering technique, (e) reference frequency multiplication technique, (f) current-mode DAC based compensation technique, (g) finite-impulse-response-embedded (FIR-embedded) noise filtering technique, and (h) space-time averaging technique.
    Fig. 16. Quantization noise suppression techniques: (a) sub-integer-N divider technique, (b) phase-interpolator (PI) based compensation technique, (c) DTC-based compensation technique, (d) phase-domain quantization noise filtering technique, (e) reference frequency multiplication technique, (f) current-mode DAC based compensation technique, (g) finite-impulse-response-embedded (FIR-embedded) noise filtering technique, and (h) space-time averaging technique.
    (Color online) ILPLL: (a) Block diagram of the basic ILPLL and the principle of the phase noise suppression of the ILPLL, (b) schematic of DILO and SILO with their injection timing, (c) ILPLL with injection timing calibration, and (d) conceptual block diagram of the ILPLL with adaptive injection timing alignment techniques.
    Fig. 17. (Color online) ILPLL: (a) Block diagram of the basic ILPLL and the principle of the phase noise suppression of the ILPLL, (b) schematic of DILO and SILO with their injection timing, (c) ILPLL with injection timing calibration, and (d) conceptual block diagram of the ILPLL with adaptive injection timing alignment techniques.
    (Color online) SSPLL: (a) block diagram of the integer-N SSPLL, (b) timing diagram and the transfer characteristics of the SSPD/SSCP, (c) simplified block diagram of the fractional-N SSPLL, and (d) simplified block diagram of the digital SSPLL.
    Fig. 18. (Color online) SSPLL: (a) block diagram of the integer-N SSPLL, (b) timing diagram and the transfer characteristics of the SSPD/SSCP, (c) simplified block diagram of the fractional-N SSPLL, and (d) simplified block diagram of the digital SSPLL.
    SPLL: simplified block diagram of (a) the integer-N SPLL and (b) fractional-N SPLL.
    Fig. 19. SPLL: simplified block diagram of (a) the integer-N SPLL and (b) fractional-N SPLL.
    ArchitectureProsConsSuitable application scenarios
    CPPLLSimple and robust1. CP-induced in-band phase noise is multiplied by N2 (N is division ratio) 2. Divider noise contributes in-band phase noise 1. Jitter and PLL power requirements are not stringent 2. Generates low-jitter clock without ultra-low jitter reference clock
    ILPLLBoth in-band and outband phase noise are suppressed simultaneouslyLarge spur induced at large division ratio NGenerates ultra-low-jitter clock with small N and ultra-low-jitter reference clock
    SSPLL1. Ultra-low in-band phase noise 2. No divider-induced phase noise Narrow PD monotonic input rangeGenerates high frequency (e. g. > 20 GHz) ultra-low-jitter clock with large N and ultra-low-jitter reference clock
    SPLL1. Ultra-low in-band phase noise 2. Wider PD monotonic input range than that of SSPLL Divider-induced phase noise still existsGenerates low frequency (e. g. < 10 GHz) ultra-low-jitter clock with large N and ultra-low-jitter reference clock
    Table 1. Summary of the features of the AMS-PLL architectures