• Journal of Semiconductors
  • Vol. 41, Issue 2, 022405 (2020)
Ruiqi Luo1、2、3, Xiaolei Chen4, and Yajun Ha1
Author Affiliations
  • 1School of Information Science and Technology, ShanghaiTech University, Shanghai 201210, China
  • 2Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
  • 3University of Chinese Academy of Sciences, Beijing 100049, China
  • 4Intel Singapore, Singapore 339510, Singapore
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    DOI: 10.1088/1674-4926/41/2/022405 Cite this Article
    Ruiqi Luo, Xiaolei Chen, Yajun Ha. A routing algorithm for FPGAs with time-multiplexed interconnects[J]. Journal of Semiconductors, 2020, 41(2): 022405 Copy Citation Text show less
    Island-style architecture, which is the base of TM-ARCH with the time-multiplexed interconnects.
    Fig. 1. Island-style architecture, which is the base of TM-ARCH with the time-multiplexed interconnects.
    (a) Signals and occupy a wire at different time. (b) In time domain, and do not overlap. (c) TM switches’ different states.
    Fig. 2. (a) Signals and occupy a wire at different time. (b) In time domain, and do not overlap. (c) TM switches’ different states.
    Routing resource graph of TM-ARCH architecture.
    Fig. 3. Routing resource graph of TM-ARCH architecture.
    Pseudo code for computing the occupation bitmaps.
    Fig. 4. Pseudo code for computing the occupation bitmaps.
    Pseudo code for computing the congestion cost.
    Fig. 5. Pseudo code for computing the congestion cost.
    Pseudo code for computing the congestion cost.
    Fig. 6. Pseudo code for computing the congestion cost.
    (Color online) The TM-ARCH and TM-ROUTER evaluation framework.
    Fig. 7. (Color online) The TM-ARCH and TM-ROUTER evaluation framework.
    Routing scheduleValue
    0.5 in the first and the second routing iteration; 1.3 times its previous value from the third iteration onwards.
    1.0 for all the iterations.
    Table 1. Resource utilization of the system.
    Feature parameterValue/specification
    LUT size4
    Logic block size10
    Logic block inputs22
    Amount of bias between horizontal and vertical channelsNo bias
    Uniformity of routing channels in the same directionUniform
    Aspect ratio1 : 1 (Assuming square logic blocks)
    Segmentation distribution100% length 4 wires
    Switch types usedUni-directional single driver switches
    Switch block topologyWilton
    Switch block internal population100%
    Connection block internal population100%
    Table 2. Main Features of Baseline FPGA Architecture.
    Parameter
    Alu44848303626
    Apex26262363422
    Apex46464503628
    Bigkey4444323230
    Clma7876744834
    Des4442343232
    Diffeq3836343230
    Dsip3836303030
    Elliptic625852N.A.34
    Ex10107474604034
    Ex5p6868483422
    Frisc7474444040
    Misex35454422622
    Pdc90901286070
    S2983434282820
    S384174848502622
    S38584.15050482622
    Seq6060482622
    Spla7472N.A.5234
    Tseng4646403432
    Geo.Mean5655443429
    Reduction–1.78%–21.43%–39.28%–48.21%
    Table 3. Minimum channel width for different values.
    Parameter
    1st2nd1st2nd3rd4th
    Alu494.594.6756.0429.644.190.45
    Apex297.092.4267.8225.322.170.21
    Apex487.3510.5628.1356.969.451.00
    Bigkey93.654.7761.5728.134.770.00
    Clma96.502.9768.8625.692.830.12
    Des90.089.1563.1624.616.501.96
    Diffeq95.973.8074.3118.473.710.10
    Dsip94.704.2859.7031.894.040.18
    Elliptic95.354.4687.517.363.650.73
    Ex101090.048.6723.6564.197.980.51
    Ex5p82.6314.8521.7056.9812.711.99
    Frisc86.8712.0668.2318.5010.581.41
    Misex393.095.6052.1933.604.640.80
    Pdc95.094.3646.9342.923.880.42
    S29885.8213.4863.2121.009.763.16
    S3841792.876.6065.0924.775.830.67
    S38584.197.411.8873.3019.911.590.26
    Seq97.502.2069.2424.661.990.17
    Spla95.983.6049.2041.063.310.25
    Tseng96.483.3488.496.822.350.73
    Geo.Mean92.855.1755.8326.194.490.51
    Table 4. Percentages (%) of wire used in each individual microcycle for 20 benchmark circuits with .
    Parameter
    Alu4583.31583.31363.31443.23323.45
    Apex2743.90743.90463.69443.69263.65
    Apex4763.80763.80583.13403.20323.20
    Bigkey521.80521.87381.80381.80381.80
    Clma946.74946.74886.63586.70446.70
    Des522.8648N.A.402.78382.85382.85
    Diffeq464.44444.51404.37384.44364.37
    Dsip461.73441.73361.80361.80361.80
    Elliptic746.22705.52625.66N.A.N.A.405.37
    Ex1010884.42884.42724.4948N.A.404.42
    Ex5p823.55823.55583.34403.23263.37
    Frisc887.63887.63527.42487.42487.49
    Misex3643.13643.13503.06323.20263.27
    Pdc1085.261085.261544.49724.49844.49
    S29840N.A.40N.A.346.14346.17246.07
    S38417584.68584.47604.47324.61264.40
    S38584.1603.71603.7158N.A.323.64263.65
    Seq723.13723.13583.06323.20263.06
    Spla884.46884.46N.A.N.A.624.14404.07
    Tseng564.43524.43484.43404.43384.43
    Geo.Mean663.90653.95533.83413.75353.85
    ReductionN.A.N.A.–1.51%1.28%–19.69%–1.79%–37.87%–3.84%-46.97%-1.28%
    Table 5. Minimum channel width for different values.
    Ruiqi Luo, Xiaolei Chen, Yajun Ha. A routing algorithm for FPGAs with time-multiplexed interconnects[J]. Journal of Semiconductors, 2020, 41(2): 022405
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