• Journal of Semiconductors
  • Vol. 41, Issue 2, 022405 (2020)
Ruiqi Luo1、2、3, Xiaolei Chen4, and Yajun Ha1
Author Affiliations
  • 1School of Information Science and Technology, ShanghaiTech University, Shanghai 201210, China
  • 2Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China
  • 3University of Chinese Academy of Sciences, Beijing 100049, China
  • 4Intel Singapore, Singapore 339510, Singapore
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    DOI: 10.1088/1674-4926/41/2/022405 Cite this Article
    Ruiqi Luo, Xiaolei Chen, Yajun Ha. A routing algorithm for FPGAs with time-multiplexed interconnects[J]. Journal of Semiconductors, 2020, 41(2): 022405 Copy Citation Text show less
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    [4] J Luu, I Kuon, P Jamieson et al. VPR 5.0: FPGA CAD and architecture exploration tools with single-driver routing, heterogeneity and process scaling. ACM Trans Reconfig Technol Syst, 4, 32(2011).

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    [8] M Shen, W Zhang, G Luo et al. Serial-equivalent static and dynamic parallel routing for FPGAs. IEEE Trans Comput-Aid Des Integr Circuits Syst(2018).

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    Ruiqi Luo, Xiaolei Chen, Yajun Ha. A routing algorithm for FPGAs with time-multiplexed interconnects[J]. Journal of Semiconductors, 2020, 41(2): 022405
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