[1] S. B. Sisler, J. P. Bonn, R. C. Whiteside. Steps per wafer reduction for photolithographic tool productivity improvement[C]. Advanced Semiconductor Manufacturing Conference and Workshop, IEEE/SEMI, 1997. 91～97
[2] Henrik Sjberg, Jean-Michel Chauvet, Jan Hrkesj et al.. Pattern accuracy and throughput optimization for an SLM-based 248-nm DUV laser mask pattern generator[C]. Proc. SPIE, 2004, 5446: 632～642
[3] Albert V. Ferris-Prabhu. An algebraic expression to count the number of chips on a wafer[J]. IEEE Circuits and Devices Magazine, 1989, 5(1): 37～39
[4] Chen-Fu Chien, Shao-Chung Hsu, Chinh-Ping Chen. An iterative cutting procedure for determining the optimal wafer exposure pattern[J]. IEEE Trans. Semiconductor Manufacture, 1999, 12(3): 375～377
[5] Chen-Fu Chien, Shao-Chung Hsu, Jing-Feng Deng. A cutting algorithm for optimizing the wafer exposure pattern[J]. IEEE Trans. Semiconductor Manufacture, 2001, 14(2): 157～162
[7] Martin van den Brink, Hans Jasper, Steve Slonaker et al.. Step-and-scan and step-and-repeat, a technology comparison[C]. SPIE Symposium on Microlithography, 1996. 10~15
[8] Naoto Sano, Kazuhiro Takahashi, Hitoshi Nakano et al.. 193 nm step and scan lithography[C]. Proc. SPIE, 2000, 4000: 532～541
