A high performance algorithm to optimize the wafer exposure field layout is presented to improve the lithographic machine performance. The size of the best exposure field is calculated from the size of the chip, extremely close to the maximum size of the exposure field of the lithographic machine, so the utilization ratio of exposure system is increased. The offset layout of the exposure field is implemented to decrease the overlap of exposure fields in edge area of the wafer, which increases the lithography throughput. With the adoption of two optimization criterions, throughput prior and yield prior, the exposure field layout is optimized for both throughput and yield. And the algorithm is used in the exposure process in a wafer fabrication laboratory, with the throughput prior criterion, and the practical viability of this approach is validated while taking the parameters of the chip production as the example. The overlap of the exposure field decreases by 10%, while the number of inner fields keeps steady. For the yield prior criterion the overlap of inner field increases by 10%, while the total number of exposure fields decrease accordingly and the chip's throughput and yield are enhanced.