Fig. 1. History of the traffic among human beings¹.

Fig. 2. Progresses in the optical communication network².

Fig. 3. Demonstration of the first optical grating connected to silicon waveguides by Luxtera. Figure reproduced from ref.⁶, under a Creative Commons Attribution License.

Fig. 4. (a–c) SEM images of a single-mode strip waveguide cross-section at different orientations. (d, e) Bending loss spectra for TE and TM polarizations, respectively. Figure reprinted with permission from ref.¹⁴, Optical Society of America.

Fig. 5. Schematic of VCSEL with Si HCG as bottom mirror. (a) Tilted-view of VCSEL cross-section with circulating red arrows indicating optical cavity. (b) The VCSEL employs a proton implant-defined aperture for current confinement, indicated by red curved lines between contacts. Figure reprinted with permission from ref.²⁷, Optical Society of America.

Fig. 6. Schematic layer structure of an InAs/GaAs QD laser on a Ge-on-Si substrate. Figure reprinted with permission from ref.³¹, Optical Society of America.

Fig. 7. SEM photographs of nano-scale Si/SiO₂ waveguides. (a, b) Multiply coupled micro-rings and their magnified ones. (c) Sharp taper. Figure reprinted with permission from ref.¹⁰, SPIE.

Fig. 8. (a) Schematic showing the operating principle of the AWG. (b) Photomicrograph of the AWG with about 1.4 mm square and eight wavelength channels. (c) Filter spectral characteristics. Figure reprinted with permission from: (b, c) ref.³⁸, OKI Corporate.

Fig. 9. Basic block diagram of an optical link including a transmitter and receiver.

Fig. 10. 50 Gb/s Si photonics transmit module. (a) and (b) are transmitter and receiver, respectively, with wavelength division multiplexing. Figure reproduced from ref.⁴³, Intel.

Fig. 11. Silicon photonics shipments, for datacenter (in units) 2019-2025e. (Source: Silicon Photonics report, Yole Développement, 2020)

Fig. 12. Si photonic MCM. (a) Photonic integrated circuit (PIC) with flip-chip mounted laser die and edge-coupled waveguide. (b) Logic, HMC and PIC mounted directly to a BGA substrate. (c) Logic and HBM mounted on a high-density interposer with micro-bumps. (d) Cut-away revealing copper pillar, flip-chip, BGA and optoelectronic interconnections. Figure reprinted with permission from ref.⁵², IBM.

Fig. 13. IBM Si CWDM 4 × 25 Gb/s die. (a) Photograph of CMOS integrated Si photonics chip. (b) Die with an array of 100 μm Pb-free flip-chip bumps on a 200 μm pitch. Two optical I/Os are seen at the bottom of the die. (c) Transmitter and receiver elements along with their eye diagrams Figure reprinted with permission from ref.⁵², IBM.

Fig. 14. Schematic cross-section of 45 nm SOI CMOS process based Si photonic platform with photonic as well as electronic devices at the front end and bump at the back end. Figure reprinted with permission from ref.⁵⁶, IEEE.

Fig. 15. Photograph of "Zero-change" SOI platform die. (a) SoC including a RISC-V processor, SRAM based cache memory and DWDM optical I/Os. (b) WDM transceivers. (c) Key photonic devices of an optical link. Figure reprinted with permission from ref.¹¹, Optical Society of America. Development timeline in Fig. 3, ref.¹¹ has been omitted here.

Fig. 16. 40 Gb/s transmitters. (a) Micrograph of the 40 Gb/s NRZ transmitter. (b) NRZ transmission eye-diagram. Figure reprinted with permission from ref.¹¹, Optical Society of America. Figs. 7(b) and 7(d) in ref.¹¹ have been omitted here.

Fig. 17. (a) Whole part of optical I/O core chip. (b, c) Cross-sectional views of receiver and transmitter, respectively. Figure reprinted with permission from ref.⁶¹. AIOCORE.

Fig. 18. Cross-sectional view of Si photonics integrated circuit with FP-LD. Figure reprinted with permission from ref.⁶⁰, The Institute of Electronics, Information and Communication Engineers.

Fig. 19. Transmission characteristics of the optical I/O core with two kinds of MMFs. Figure reprinted with permission from ref.⁶⁰, The Institute of Electronics, Information and Communication Engineers.

Fig. 20. Schematic of typical optical switch topologies. (a) Crossbar. (b) PILOSS. (c) Beneš. (d) Switch-and-select. Figure reprinted with permission from ref.⁶⁶, Optical Society of America.

Fig. 21. (a) Example of multi-ring network. (b) 4-degree ROADM node configuration connecting two ring networks. Figure reprinted with permission from ref.⁶⁹, NTT Technical Review.

Fig. 23. (a) Two cases of reconfiguring optical paths in photonic networks with CDC-ROADMs. (b) Schematic of CDC-ROADM. (c) TPA consisting of multiple optical switch modules. (d) Configuration of 8 × 8 multi-cast optical switch. Figure reprinted with permission from ref.⁷⁵, IEEE.

Fig. 26. 32 × 32 Si TO MZI-based PILOSS switch. Figure reprinted with permission from ref.⁸⁴, Optical Society of America.

Fig. 27. Transmission characteristics of the six sampled optical paths 1-12, 1-20, 1-32, 32-1, 32-13, and 32-19. (a) Path on the PILOSS switch matrix. (b) On-chip loss. Inset in (b) shows the spectral passband of the path 32-1. Figure reprinted with permission from ref.⁸⁴, Optical Society of America.

Fig. 28. 32 × 32 Si EO MZI-based Beneš switch. Figure reprinted with permission from ref.⁹⁰, under a Creative Commons Attribution 4.0 International License.

Fig. 29. (a) Schematic configuration of hybrid Si free-space source with integrated beam steering. (b) Layout of the overall devices. Figure reprinted with permission from ref.¹⁰⁴, SPIE.

Fig. 30. (a) Measured beam profiles at 1555 nm wavelength as the beam was swept across the field of view in the ψ axis at 1° increments. (b) Plots of the 2D beam profiles at the corners and center of the field of view. Figure reprinted with permission from ref.¹⁰⁹, Optical Society of America.

Fig. 31. (a) Schematic of the solid-state LiDAR system with transmitting and receiving optical phased arrays. (b) 3D picture of the optical phased array. (c–e) SEM images of phase shifter, magnified one and antenna, respectively. (f) Optical micrograph of the device. Figure reprinted with permission from ref.¹¹⁷, Optical Society of America.

Table 1. Silicon photonics supply chain for optical transceivers⁴¹. (Source: Silicon Photonics report, Yole Développement, 2020)

Table 2. Major 2017 foundries (Pure-Play and IDM (integrated device manufacturer)). Table reprinted with permission from ref.⁴².