Fig. 1. (Color online) Schematic representation of the bottom gate bottom contact organic thin film transistor.
Fig. 2. (Color online) Schematic representation of the mixed mode analysis of ATLAS for circuit implementation.
Fig. 3. (Color online) Experimental[9] and simulated device results: (a) output and (b) transfer characteristics curve.
Fig. 4. (Color online) Transfer characteristics curve validity of simulated device through model[21] and experimental[9].
Fig. 5. (Color online) (a) The basic circuitry for logic high organic-PT. (b) Variation of output voltage with respect to time through MATLAB. (c) Simulation result for the logic high signal with the input supply of 5 V.
Fig. 6. (Color online) (a) The basic circuitry for logic low organic-PT. (b) working principle of the proposed model for logic low signal. (c) Variation of output voltage with respect to time through MAT Lab. (d) Simulation result for the logic low signal with the input supply of 5 V.
Parameter | Value |
---|
Gate electrode (Si) | 150 nm | Bottom gate (SiO2), tox | 100 nm | OSC thickness (tosc) (pentacene)
| 200 nm | Width of S/D (ts/td) (gold)
| 80 nm | Active layer length (L)
| 25 µm | Active layer width (W)
| 800 µm |
|
Table 1. Device parameters for the organic material based device[9].
Parameter | Experiment[9] | Simulated |
---|
µ(cm2/(V·s))
| 0.02 | 0.019 | Ion/Ioff | 3.2 × 103 | 5.1 × 103 | SS (V/dec.) | 2.0 | 2.3 | gm (µS)
| 0.044 | 0.041 | VTH(V)
| – 2.0 | – 2.1 |
|
Table 2. Electrical parameter comparison of pentacene-based single gate organic thin film transistor.
Parameter | Value |
---|
W/L | 800/25 | Cox | 0.345 × 10–9 F/cm2 | µ | 0.012 cm2/(V·s)
| γ | 2.1[21] | To | 465 K[21] | Vt | –2.1 V |
|
Table 3. Fitting parameters for the transfer characteristics using the model through MATLAB[21].
Parameter | Analytical | Simulated |
---|
Output voltage (V) | 2.89 | 3 |
|
Table 4. Comparison between analytical and simulation parameters for logic high transfer signal.
Parameter | Value |
---|
W/L (T1)
| 5000 μm/100 μm
| W/L (T2)
| 300 μm/100 μm
| W/L (T3)
| 300 μm/100 μm
| W/L (T4)
| 5000 μm/100 μm
| W/L (T5)
| 300 μm/100 μm
| COLED | 0.6 nF |
|
Table 5. Dimensions for the simulated parameters of the proposed inverter design.
Parameter | Analytical | Simulated |
---|
Output voltage (V) | 0.012 | 0.5 |
|
Table 6. Comparison between analytical and simulation parameters for logic low transfer signal.