• Laser & Optoelectronics Progress
  • Vol. 59, Issue 9, 0922006 (2022)
Yanli Li, Xianhe Liu, and Qiang Wu*
Author Affiliations
  • School of Microelectronics, Fudan University, Shanghai 201203, China
  • show less
    DOI: 10.3788/LOP202259.0922006 Cite this Article Set citation alerts
    Yanli Li, Xianhe Liu, Qiang Wu. Evolution and Updates of Advanced Photolithography Technology[J]. Laser & Optoelectronics Progress, 2022, 59(9): 0922006 Copy Citation Text show less
    References

    [1] Wu Q, Hu H Y, He W M et al[M]. Photolithography process near the diffraction limit(2020).

    [2] Markle D. A new projection printer[J]. Solid State Technology, 17, 50-53(1974).

    [3] Offner A. New concepts in projection mask aligners[J]. Optical Engineering, 14, 130-132(1975).

    [4] ASML. ASML Official website[EB/OL]. https://www.asml.com/en/products/duv-lithography-systems/twinscan-nxt1970ci

    [5] Teruyoshi Y, Eiichi K. Novel optimization method for antireflection coating[J]. Proceedings of SPIE, 2726, 564-572(1996).

    [6] Lucas K D, Cook C, Lee K et al. Antireflective coating optimization techniques for sub-0.2-‍μm geometries[J]. Proceedings of SPIE, 3677, 457-467(1999).

    [7] Sakaguchi T, Enomoto T, Nakajima Y. Bottom anti-reflective coatings for 193-nm bilayer system[J]. Proceedings of SPIE, 5753, 619-626(2005).

    [8] Lin B J. Off-axis illumination: working principles and comparison with alternating phase-shifting masks[J]. Proceedings of SPIE, 1927, 89-100(1993).

    [9] Kim B, Park C H, Ryoo M et al. Application of phase-edge PSM for narrow logic gate[J]. Proceedings of SPIE, 3873, 943-952(1999).

    [10] Gabor A H, Bruce J A, Chu W et al. Subresolution assist feature implementation for high-performance logic gate-level lithography[J]. Proceedings of SPIE, 4691, 418-425(2002).

    [11] Chen J F, Laidig T L, Wampler K E et al. Practical method for full-chip optical proximity correction[J]. Proceedings of SPIE, 3051, 790-803(1997).

    [12] Kling M E, Lucas K D, Reich A J et al. 0.25-μm logic manufacturability using practical 2D optical proximity correction[J]. Proceedings of SPIE, 3334, 204-214(1998).

    [13] Ozawa K, Thunnakart B, Kaneguchi T et al. Effect of azimuthally polarized illumination imaging on device patterns beyond 45 nm node[J]. Proceedings of SPIE, 6154, 61540C(2006).

    [14] Burnett J H, Kaplan S G, Shirley E L et al. High-index materials for 193 nm immersion lithography[J]. Proceedings of SPIE, 5754, 611-621(2005).

    [15] Benndorf M, Warrick S, Conley W et al. Integrating immersion lithography in 45-nm logic manufacturing[J]. Proceedings of SPIE, 6520, 652007(2007).

    [16] Hsu S, Chen L Q, Li Z P et al. An innovative source-mask co-optimization (SMO) method for extending low k1 imaging[J]. Proceedings of SPIE, 7140, 714010(2008).

    [17] Yoshimochi K, Nagahara S, Takeda K et al. Challenges for low-k1 lithography in logic devices by source mask co-optimization[J]. Proceedings of SPIE, 7640, 76401K(2010).

    [18] Funato S, Kawasaki N, Kinoshita Y et al. Application of photodecomposable base concept to two-component deep-UV chemically amplified resists[J]. Proceedings of SPIE, 2724, 186-195(1996).

    [19] Padmanaban M, Bae J B, Cook M M et al. Application of photodecomposable base concept to 193-nm resists[J]. Proceedings of SPIE, 3999, 1136-1146(2000).

    [20] Robertson S A, Reilly M, Biafore J J et al. Negative tone development: gaining insight through physical simulation[J]. Proceedings of SPIE, 7972, 79720Y(2011).

    [21] Gonsalves K E, Thiyagarajan M, Dean K. Newly developed polymer bound photoacid generator resist for sub-100-nm pattern by EUV lithography[J]. Proceedings of SPIE, 5753, 771-777(2005).

    [22] Cho Y, Gu X Y, Hagiwara Y et al. Polymer-bound photobase generators and photoacid generators for pitch division lithography[J]. Proceedings of SPIE, 7972, 797221(2011).

    [27] Wu Q, Li Y L, Zhao Y H. The evolution of photolithography technology, process standards, and future outlook[C](2020).

    [29] Trouiller Y, Belledent J, Chapon J D et al. Gate imaging for 0.09-μm logic technology: comparison of single exposure with assist bars and the CODE approach[J]. Proceedings of SPIE, 5040, 1231-1240(2003).

    [30] Brist T E, Bailey G E. Effective multicutline QUASAR illumination optimization for SRAM and logic[J]. Proceedings of SPIE, 5042, 153-159(2003).

    [31] LaPedus M. Intel drops 157-nm tools from lithography roadmap[EB/OL]. https://www.eetimes.com/intel-drops-157-nm-tools-from-lithography-roadmap/

    [32] Lin Q, Hisamura T, Chong N et al. Optimization of the EUV contact layer process for 7 nm FPGA production[J]. Proceedings of SPIE, 11609, 116090V(2021).

    [33] Zhang S J, Shen M H, Xu Y et al. Performance comparison between attenuated PSM and opaque MoSi on glass (OMOG) mask in sub-32 nm litho process[J]. ECS Transactions, 44, 249-256(2012).

    [34] Sakamoto R, Ho B C, Fujitani N et al. Development of under layer material for EUV lithography[J]. Proceedings of SPIE, 7969, 79692F(2011).

    [35] Wu A W, Bayana H, Foubert P et al. Improving EUV underlayer coating defectivity using point-of-use filtration[J]. Proceedings of SPIE, 11326, 113261Z(2020).

    [36] Wu Q, Li Y L, Yang Y S et al. The law that guides the development of photolithography technology and the methodology in the design of photolithographic process[C](2020).

    [37] Wu Q, Li Y L, Yang Y S et al. A study of image contrast, stochastic defectivity, and optical proximity effect in EUV photolithographic process under typical 5 nm logic design rules[C](2020).

    [38] Cornelissen S A, Bierden P A, Bifano T G. Development of a 4096 element MEMS continuous membrane deformable mirror for high contrast astronomical imaging[J]. Proceedings of SPIE, 6306, 630606(2006).

    [39] Li Y L, Wu Q, Chen S M. A simulation study for typical design rule patterns in 5 nm logic process with EUV photolithographic process[J]. Journal of Microelectronic Manufacturing, 2, 1-8(2019).

    [40] Civay D, Hosler E, Chauhan V et al. EUV telecentricity and shadowing errors impact on process margins[J]. Proceedings of SPIE, 9422, 94220Z(2015).

    [41] van Schoot J, van Setten E, Troost K et al. High-NA EUV lithography exposure tool: program progress[J]. Proceedings of SPIE, 11323, 1132307(2020).

    [42] Ii O W, Wong K, Parks V et al. Improved Ru/Si multilayer reflective coatings for advanced extreme-ultraviolet lithography photomasks[J]. Proceedings of SPIE, 9776, 977619(2016).

    [43] de Bisschop P, Hendrickx E. Stochastic printing failures in EUV lithography[J]. Proceedings of SPIE, 10957, 109570E(2019).

    [44] Li Y L, Zhu X N, Yu S F et al. A study of the advantages to the photolithography process brought by the high NA EUV exposure tool in advanced logic design rules[C](2021).

    [45] ASML. ASML Official website[EB/OL]. https://www.asml.com/en/products/euv-lithography-systems/twinscan-nxe-3600d

    [46] Christophe F. EUV products and business opportunity[EB/OL]. https://www.asml.com/-/media/asml/files/investors/investor-days/2021/asml-investor-day-2021_business-line-euv---christophe-fouquet.pdf?rev=d2ada06e13964241a3cf69d0d758f1722021

    [47] van Schoot J, van Ingen Schenau K, Valentin C et al. EUV lithography scanner for sub-8 nm resolution[J]. Proceedings of SPIE, 9422, 94221F(2015).

    [48] Ahn C N, Nam D S, Seong N et al. Optical design of EUV attenuated PSM for contact-hole applications[J]. Proceedings of SPIE, 11609, 116090D(2021).

    [49] Wang X L, Tasdemir Z, Mochi I et al. Progress in EUV resists towards high-NA EUV lithography[J]. Proceedings of SPIE, 10957, 109570A(2019).

    Yanli Li, Xianhe Liu, Qiang Wu. Evolution and Updates of Advanced Photolithography Technology[J]. Laser & Optoelectronics Progress, 2022, 59(9): 0922006
    Download Citation