Double-balanced mixer based on monolayer graphene field-effect transistors

Min Wu; Weida Hong; Guanyu Liu; Jiejun Zhang; Ziao Tian; Miao Zhang

doi:10.1088/1674-4926/43/5/052002

Abstract

Graphene field-effect transistors (GFET) have attracted much attention in the radio frequency (RF) and microwave fields because of its extremely high carrier mobility. In this paper, a GFET with a gate length of 5 μm is fabricated through the van der Walls (vdW) transfer process, and then the existing large-signal GFET model is described, and the model is implemented in Verilog-A for analysis in RF and microwave circuits. Next a double-balanced mixer based on four GFETs is designed and analyzed in advanced design system (ADS) tools. Finally, the simulation results show that with the input of 300 and 280 MHz, the IIP3 of the mixed signal is 24.5 dBm.

1. Introduction

Since the discovery of monolayer graphene^[1], graphene has become an attractive candidate to replace or supplement traditional semiconductors due to its excellent electrical and mechanical properties, as well as high compatibility with standard processes. Compared with semiconductors, only one atomic layer thickness, ultra-high carrier mobility^[2-4] and higher saturation velocity^[5] make it possible to produce graphene field-effect transistors (GFETs) with higher cut-off frequencies^[6]. Bipolar transmission is a main feature of GFETs, that is, the conductivity of GFETs can be controlled by holes or electrons. It results in a ‘V’-shaped transfer characteristic (I_ds–V_gs)^[1]. Due to its unique ambipolar transport properties and extremely high mobility, graphene provides a wide range of applications for radio frequency and microwave fields.

Because of these excellent characteristics, graphene was used in practice, such as frequency multipliers^{[7, 8]}, voltage amplifiers^[9], ring oscillators^[10], and mixers^[11]. Graphene is even being studied in fields related to RF switches^[12] and memory^[13]. The study of graphene mixers is particularly concerned. Mixers are essential for almost all telecommunications and radar equipment, and limit the intermodulation performance of the receiver front end. Schottky barrier diodes and active FETs are the most commonly used mixer elements in microwave systems, but the linearity of these mixers is very low due to the strong nonlinearity of these devices. In contrast, the linear output characteristics of graphene makes it particularly suitable for such circuit applications. Although unsaturation is detrimental to traditional amplifier circuits, it is an advantage of resistive mixers now. Palacios et al. prepared a graphene resistive mixer for the first time using the characteristics of graphene bipolar transport. Conversion loss was 30–40 dB and IIP3 was 13.8 dBm at 10 MHz^[14]. In Ref. [15], the first graphene integrated circuit work was to realize a resistive mixer. Moon et al. also used the structure to prepare a graphene mixer, and showed the IIP3 of 22 dBm at a LO power of –3.5 dBm^[16].

This paper explores the potential of graphene mixers. In order to further improve the linearity of the mixers, a graphene double-balanced mixer with four GFETs with cross-coupling structure is designed. The circuit structure is based on a proposed GFET large-signal model in ADS for circuit simulation^[17]. And it achieves IIP3 of 24.5 dBm with a LO signal of –2 dBm at 280 MHz. The main performance characteristics of the double-balanced GFET mixer are compared with CMOS technologies and the reported GFET mixer.

2. Monolayer graphene field-effect transistor

2.1. GFET fabrication

In this work, the transistor was fabricated on a high-resistance silicon (>10 kΩ·cm) substrate with 1µm thick silicon oxide. Monolayer graphene is grown on Ge substrate by chemical vapor deposition (CVD) method^[18], and germanium-based graphene is used as a smooth substrate. Then 50 nm Au was evaporated by UV lithography and electron beam as source and drain, next 3 nm Al was evaporated by electron beam, after that 30 nm Al₂O₃ was grown by ALD as the gate dielectric layer, and then 50 nm Au was evaporated by electron beam as the top gate electrode. Finally, the PVA solution was dripped, and after the PVA was dried, the metal (source and drain)/oxide layer (gate dielectric layer)/metal (gate) sandwich layer was transferred to the SiO₂/Si (>10 kΩ·cm) with graphene channel. A GFET is formed on the substrate, and the graphene channel forms a vdW contact with the contact electrode. This transfer process reduces the damage of photolithography to the graphene channel and the contact resistance, which can have better device performance^[19-21].

Fig. 1(a) shows a 3D schematic diagram of GFETs on SiO₂/Si. Fig. 1(b) is an optical microscope image of GFETs with a dual-finger gate and ground–signal–ground (GSG) structure for the RF test. The gate length L_g is 5 μm and gate width W is 70 μm. Fig. 1(c) presents the transfer characteristic curve (I_ds–V_gs) of the GFET at V_ds = 0.1 to 1 V and the Dirac point was observed to be located at around V_dirac = –0.2 V. We adopt standard de-embedding method for avoiding the influence of parasitic capacitance and inductance of the GSG pad^[22]. And we prepared the open circuit and short circuit structure of the same device size to ensure reliable de-embedding results. In Fig. 1(d), we show the current gain |H₂₁| and the unilateral gain |U| of the GFET with L_g = 5 μm and W = 70 μm at V_ds= 0.8 V. The highest (intrinsic) maximum oscillation frequency f_MAX of ~603 MHz and the highest (intrinsic) cutoff frequency f_T of ~368 MHz are found.

Figure 1.(Color online) (a) Schematic of top-gated Al₂O₃/monolayer graphene FET. (b) Photograph of a dual-finger gate 5-µm-length and 70-µm-wide graphene FET. (c) Measured data for the I_ds–V_gs characteristic curves at V_ds = 0.1 to 1 V. (d) Current gain, |H₂₁|, and unilateral gain, U, with de-embedding at V_ds = 0.8 V.

2.2. A large-signal model of monolayer GFET

During circuit design, accurate GFET models are required to predict device and circuit performance. The small signal model cannot describe the nonlinear effects of the device to meet the simulation requirements of nonlinear circuits such as mixers and oscillators. However, the large signal model can give the complete characteristics of the device. Several models of GFET were developed recently^[23-27]. This article uses a monolayer GFET large-signal behavior model developed by Jan Stake et al. and based on the drift-diffusion equation^[17].

In this model, the graphene quantum capacitance will be ignored when the thickness of the gate dielectric layer is greater than 10 nm. And we also ignore the quantum capacitance of graphene. The model can be implemented by Verilog-A language in ADS environment.

The schematic of a monolayer GFET large-signal model is presented in Fig. 2. The current in the channel can be expressed as:

Figure 2.Large-signal model of a GFET. C_pd, C_pg, L_g, L_d and L_s are pad parasitic capacitance values and inductances, R_g is the gate resistance, and R_s and R_d are the source and drain resistances including contact and access resistances.

$ {I}_{\mathrm{d}\mathrm{s}1}=\frac{{\mu }_{\mathrm{e}}{V}_{\mathrm{d}\mathrm{i}\mathrm{r}\mathrm{a}\mathrm{c}}{Q}_{0}}{\sqrt{1+\dfrac{{\mu }_{\mathrm{e}}\left|{V}_{\mathrm{g}\mathrm{s}}{V}_{\mathrm{d}\mathrm{s}}\right|}{L \overline {{v}_{\mathrm{s}\mathrm{a}\mathrm{t}}}}}}\frac{W}{L}f\left(\overline {{V}_{\mathrm{g}\mathrm{s}}}, \overline {{V}_{\mathrm{g}\mathrm{d}}}\right) $  (1)

with V_gs > 0, V_gd > 0.

$ \begin{split}{I}_{\mathrm{d}\mathrm{s}2}= & \dfrac{{\mu }_{\mathrm{e}}{V}_{\mathrm{d}\mathrm{i}\mathrm{r}\mathrm{a}\mathrm{c}}{Q}_{0}}{\sqrt{1+\dfrac{{\mu }_{\mathrm{e}}\left|{V}_{\mathrm{g}\mathrm{s}}{V}_{\mathrm{d}\mathrm{s}}\right|}{L\overline{{v}_{\mathrm{s}\mathrm{a}\mathrm{t}}}}}}\dfrac{W}{L}f\left(\overline{{V}_{\mathrm{g}\mathrm{s}}},0\right)+\\ & \dfrac{{\mu }_{\mathrm{h}}{V}_{{\rm{dirac}}}{Q}_{0}}{\sqrt{1+\dfrac{{\mu }_{\mathrm{h}}\left|{V}_{\mathrm{g}\mathrm{s}}{V}_{\mathrm{d}\mathrm{s}}\right|}{L\overline{{v}_{\mathrm{s}\mathrm{a}\mathrm{t}}}}}}\dfrac{W}{L}f\left(0,\overline{{V}_{\mathrm{g}\mathrm{d}}}\right) \end{split}$  (2)

with V_gs > 0, V_gd < 0.

$ \begin{split}{I}_{\mathrm{d}\mathrm{s}3}= & \dfrac{{\mu }_{\mathrm{h}}{V}_{\mathrm{d}\mathrm{i}\mathrm{r}\mathrm{a}\mathrm{c}}{Q}_{0}}{\sqrt{1+\dfrac{{\mu }_{\mathrm{h}}\left|{V}_{\mathrm{g}\mathrm{s}}{V}_{\mathrm{d}\mathrm{s}}\right|}{L\overline{{v}_{\mathrm{s}\mathrm{a}\mathrm{t}}}}}}\dfrac{W}{L}f\left(\overline{{V}_{\mathrm{g}\mathrm{s}}},0\right)+\\ & \dfrac{{\mu }_{\mathrm{e}}{V}_{\mathrm{d}\mathrm{i}\mathrm{r}\mathrm{a}\mathrm{c}}{Q}_{0}}{\sqrt{1+\dfrac{{\mu }_{\mathrm{e}}\left|{V}_{\mathrm{g}\mathrm{s}}{V}_{\mathrm{d}\mathrm{s}}\right|}{L\overline{{v}_{\mathrm{s}\mathrm{a}\mathrm{t}}}}}}\dfrac{W}{L}f\left(0,\overline{{V}_{\mathrm{g}\mathrm{d}}}\right) \end{split}$  (3)

with V_gs < 0, V_gd > 0.

$ {I}_{\mathrm{d}\mathrm{s}4}=\frac{{\mu }_{\mathrm{h}}{V}_{\mathrm{d}\mathrm{i}\mathrm{r}\mathrm{a}\mathrm{c}}{Q}_{0}}{\sqrt{1+\dfrac{{\mu }_{\mathrm{h}}\left|{V}_{\mathrm{g}\mathrm{s}}{V}_{\mathrm{d}\mathrm{s}}\right|}{L\overline{{v}_{\mathrm{s}\mathrm{a}\mathrm{t}}}}}}\frac{W}{L}f\left(\overline{{V}_{\mathrm{g}\mathrm{s}}},\overline{{V}_{\mathrm{g}\mathrm{d}}}\right) $  (4)

with V_gs < 0, V_gd < 0.

Among them, the following function is defined as:

$ f\left(x,y\right)=x\sqrt{1+{x}^{2}}-y\sqrt{1+{y}^{2}}+\frac{\mathrm{l}\mathrm{n}\sqrt{1+{x}^{2}}+x}{\sqrt{1+{y}^{2}}+y} ,$  (5)

where is the saturation velocity of the carrier at the average gate voltage, C = (C_gs + C_gd )/(LW) is the gate capacitance per area, ν_F = 10⁸ cm/s and β relates to the optical phonon wavelength of the dominant scattering phonon, Q₀ (q×n₀) is the residual charge density, µ is the carrier mobility, V_dirac is the Dirac voltage, and defining: and .

Resistance between the source and drain can be expressed as:

$ {R}_{\mathrm{d}}={R}_{\mathrm{s}}={R}_{0}+{R}_{\mathrm{e}\mathrm{x}\mathrm{t}}({V}_{\mathrm{g}\mathrm{s}},{V}_{\mathrm{g}\mathrm{d}}), $  (6)

$ {R}_{\mathrm{e}\mathrm{x}\mathrm{t}}\left({V}_{\mathrm{g}\mathrm{s}},{V}_{\mathrm{g}\mathrm{d}}\right)=\frac{1+\mathrm{t}\mathrm{a}\mathrm{n}\mathrm{h}{V}_{\mathrm{g}\mathrm{s}}}{2} \frac{1+\mathrm{tanh}{V}_{\mathrm{g}\mathrm{d}}}{2} {R}_{\mathrm{e}\mathrm{x}\mathrm{t}0}, $  (7)

where R₀ is the contact resistance and R_ext0 is an extra resistance when the majority carriers are electron.

Intrinsic capacitors were extracted by S-parameters biased at Dirac voltage (V_gs = V_dirac, g_m = 0). By de-embedding the S-parameters, we can get: , , . The model parameter extraction method in Fig. 2 is the same as the method described in Ref. [17], and the parameters were extracted as shown in Table 1. The behavior model is implemented by Verilog-A and is compatible with ADS. As shown in Fig. 3, the solid lines are the measured output characteristic curve (I_ds–V_ds) of the GFET, showing excellent linearity. The dotted lines are the output characteristic curves of the GFET DC simulation. It can be seen that the model is consistent with the measurement results. The large-signal model will be applied to subsequent mixer circuit design in section 3.

Table Infomation Is Not Enable

Figure 3.(Color online) Model versus measured data for the I_ds–V_ds characteristic curves at V_gs = –3 to 3 V.

3. GFET double-balanced mixer

3.1. GFET mixer circuit design

Compared with a single GFET mixer, a graphene double-balanced mixer can have better linearity and can suppress the feedthrough of RF and LO signals^[28]. The circuit diagram of the GFET double-balanced mixer in this article is shown in Fig. 4. It consists of four GFETs with cross-coupling structure and four LC components, in which the inductance is 25 nH and the capacitance is 25 pF. The LC component has a filtering function, and LO, RF and IF are all differential signals. The four GFETs (with L_g = 5 µm, W = 70 µm) operate at V_gs = –0.6 V and V_ds = 0.8 V. And the mixer is simulated in ADS. Due to the linear characteristics of the GFET, the mixer is expected to have a high linear output.

Figure 4.Schematic of the GFET double-balanced mixer.

3.2. Simulation of the GFET double-balanced mixer

Fig. 5 shows the RF performance of the GFET double-balanced mixer. Fig. 5(a) presents the simulated conversion loss (CL) versus LO power with a minimum CL of 23 dB at 300 MHz. Fig. 5(b) is IF power versus RF power with f_LO = 280 MHz (4 dBm) and f_RF = 300 MHz. The dots in the figure are simulated data, and the line is the linear fitting, indicating that the 1 dB compression point is 6.5 dBm. Fig. 5(c) reveals the simulated two-tone spectra of the mixer. The third-order intermodulation product (IM3) is 85 dBm lower than IF with RF power of −20 dBm. According to IIP3 = RF _in + (IF – IM3)/2, IIP3 is calculated as 22.5 dBm. The fundamental and the third-order term in the output signal versus RF power are shown in Fig. 5(d). After linear fitting and expansion, the IIP3 is displayed as 24.5 dBm. In Table 2, the main performance of the mixer reported in this article is compared with the recently reported GFET mixer and CMOS mixer. It can be seen from the table that the designed mixer in this paper has more excellent linearity.

Figure 5.(Color online) RF performance of the double-balanced mixer. (a) Simulation result of conversion gain. (b) Simulation result of –1 dB compress point. (c) Simulated two-tone spectrum of the mixer. (d) Simulation result of IIP3.

Table Infomation Is Not Enable

4. Conclusion

In this work, we prepared a monolayer GFET by transfer process and assessed the DC and RF characterization. And we performed large-signal modeling on the GFET, which is written in Verilog-A and connected in ADS. A double-balanced mixer is designed based on the GFET and it provides a IIP3 of 24.5 dBm at 300 MHz. Compared with traditional CMOS mixers and GFET mixers that have been reported, it has better linearity. In addition, the operating frequency of the mixer is only limited by the f_T of the GFET, and the gate length of the GFET can be reduced to broaden the operating frequency^[34].

Acknowledgements

The authors thank National Natural Science Foundation of China (Grant Nos. 51925208, 61974157, 61851401, 62122082), Key Research Project of Frontier Science, Chinese Academy of Sciences (QYZDB-SSW-JSC021), National Science and Technology Major Project (2016ZX02301003), Science and Technology Innovation Action Plan of Shanghai Science and Technology Committee (20501130700), Strategic Priority Research Program (B) of the Chinese Academy of Sciences (XDB30030000) and Science and Technology Commission of Shanghai Municipality (19JC1415500).

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