Abstract
1. Introduction
The gradual geometrical scale down of logic devices has successfully approached the ultimate performance of silicon transistors in the past 60 years[
2D semiconductors, especially transition metal dichalcogenides (TMDC), have a satisfied thickness-dependent bandgap of 1–2 eV, which can enable lots of fascinating device applications in field-effect transistors (FETs) with the extraordinary on/off current ratio (> 108) and off-state current (< 1 pA), and atomically thin body thickness, which gives new opportunities to improve gate control and reduce the SCE main issues in ultra-scaled devices[
The static and dynamic power consumption of logic transistors are proportional to operating voltage (Vdd) and quadratic of Vdd, respectively[
According to the Boltzmann tyranny, the SS of MOSFETs at room temperature will not be lower than
Here, we will summarize the latest progress of 2D low-power logic transistors from the following aspects. First, we will give a brief discussion of the ultra-thin dielectric integration on 2D TMDC, together with analysis of interface quality from different interface passivation. Then, novel NCFETs will be discussed, including the working mechanism and device progress. Moreover, a perspective for sub-1 nm EOT and NCFETs will be discussed in the last paragraph of the corresponding section.
2. Integration of ultrathin dielectric on 2D materials
In the early days of the semiconductor industry, SiO2 has been used as a gate dielectric of MOSFETs for decades due to nearly ideal interface between Si and SiO2[
So far, the most controllable approach in semiconductor industry for low cost, high-quality, scalable dielectric deposition is atomic layer deposition (ALD)[
Figure 1.(Color online) Integrating ultra-thin high-
The surface of 2D material is pretreated by high-activity units such as plasma, ozone and electron beam to increase the nucleation sites for ALD. However, these processes involve high-energy and reactive species which will introduce the overmuch defects and interface states[
Besides, using organic film as the seeding layer to realize the conformal deposition of oxide on 2D materials, which is more amicable than the above surface functionalization and oxidized metal layer method to 2D materials because of ultra-smooth interface of organic crystal and damage-free van der Waals interaction[
Although some new techniques applied, compared with the advanced technology, high-κ dielectric with larger EOT and inferior interface quality are still one of the biggest obstacles to the application of 2D MOSFETs. Fig. 1(c) shows the requirement of high-quality dielectric on 2D materials, including smaller EOT and Dit, potential of scalable integration and so on. The organic seeding layer is one of the most promising techniques for implementing large-scale 2D integrated circuits due to damage-free interface and scalable integration potential, which are the great advantages beyond other technologies. Recent developments indicate that some organic molecules can self-limited assemble on 2D materials by van der Waals interaction with thickness of only single atomic layer[
3. Ultra-low power NC-FET based on 2D TMDC
The dielectric, as we all know, comprises a significant contribution to the power dissipation of nano devices and integrated circuits. Different from boosting gate capacitance, ferroelectric NCFETs[
The phenomenological formalism for the double-well Gibb’s free energy Uf of a single-domain ferroelectric capacitor is given as a function of the spontaneous polarization Ps:
Figure 2.(Color online) Basic concept of NC and ultra-low power NCFETs based on 2D TMDC. (a) Schematic of two capacitors in series.
According to Eq. (1), the first term
For ferroelectric materials in NCFETs application, traditional perovskite ferroelectrics like PbZrO3 (PZT), BaTiO3 (BTO), or polymers like polyvinylidene fluoride-trifluoroethylene (PVDF-TrFE) obviously become out of place due to their poor thickness scalability and CMOS process compatibility. Fortunately, ferroelectric polycrystalline HfZrO2 (HZO)[
Recent researches have shown that 2D semiconductors using ferroelectric as gate dielectric exhibit excellent performance, such as reduced SS and Vdd, etc. Yu et al. fabricated n-type MoS2 NCFETs[
The SS-Hysteresis phase diagram (Fig. 2(f)) summarizes representative reported works of 2D NCFETs with comparison with the advanced Silicon technology and ITRS requirements. According to ITRS 2.0 requirements of logic transistors released in 2015, SS will decrease to 40 mV/dec in 2024, and 25 mV/dec in 2030, shown in Fig. 2(f). Of note, apart from large hysteresis of MoS2/PVDF cases (in purple shadow), several 2D NCFETs can satisfy ITRS requirement of 40 mV/dec (even 25 mV/dec), while the difference of SS between forward and reverse sweep and hysteresis in transfer curves remain to be reduced.
Although results above have demonstrated excellent isolated device performance, NCFETs applications still face several major problems: physics behind NC effect, the highest operating frequency of NCFETs, and the fatigue characteristics and reliability of ferroelectric materials such as HZO. Recently, transient NC measurements[
4. Conclusion
2D semiconductors are promising candidates for low-power logic transistors due to their inherent advantages, such as ultimate body thickness, dangling bond free, sizable and tunable bandgap, and reasonable mobility. However, the application of 2D semiconductors remains in infancy, and more specific techniques for 2D characteristics have been developed. In this paper, low-power 2D logic transistors using ultra-thin high-κ dielectric and NCFETs are overviewed. Some recent progresses of techniques for gate dielectric with related advantages and disadvantages are reviewed. Moreover, a perspective discussion for realization of sub-1 nm EOT was followed. Then, the performance of typical 2D NCFETs are analyzed, and more researches on 2D NCFETs are summarized. At last, a prospect for further development for NCFETs is addressed.
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