• Acta Optica Sinica
  • Vol. 41, Issue 17, 1706002 (2021)
Yanjun Liu1、2、***, Yan Li1、2、*, Yuyang Liu1、2, Xiaoshuo Jia1、2, Honghang Zhou1、2, Xiaobin Hong1、2, Jifang Qiu1、2, Hongxiang Guo1、2, Yong Zuo1、2, Wei Li1、2, and Jian Wu1、2、**
Author Affiliations
  • 1School of Electronic Engineering, Beijing University of Posts and Telecommunications, Beijing 100876, China
  • 2State Key Laboratory of Information Photonics and Optical Communications, Beijing University of Posts and Telecommunications, Beijing 100876, China
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    DOI: 10.3788/AOS202141.1706002 Cite this Article Set citation alerts
    Yanjun Liu, Yan Li, Yuyang Liu, Xiaoshuo Jia, Honghang Zhou, Xiaobin Hong, Jifang Qiu, Hongxiang Guo, Yong Zuo, Wei Li, Jian Wu. Implementation of FPGA Based on High Throughput Parallel CRC-SCL Decoder of Polar Codes[J]. Acta Optica Sinica, 2021, 41(17): 1706002 Copy Citation Text show less
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    [15] Giard P, Balatsoukas-Stimming A, Müller T C et al. A multi-Gbps unrolled hardware list decoder for a systematic polar code[C]∥2016 50th Asilomar Conference on Signals, Systems and Computers, November 6-9, 2016, Pacific Grove, CA, USA., 1194-1198(2016).

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    Yanjun Liu, Yan Li, Yuyang Liu, Xiaoshuo Jia, Honghang Zhou, Xiaobin Hong, Jifang Qiu, Hongxiang Guo, Yong Zuo, Wei Li, Jian Wu. Implementation of FPGA Based on High Throughput Parallel CRC-SCL Decoder of Polar Codes[J]. Acta Optica Sinica, 2021, 41(17): 1706002
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