Polar codes belong to a coding scheme that is proved to reach the limit of channel capacity by strict mathematical methods. To apply polar codes to high-speed real-time optical communication systems, we adopt a fully-unrolled pipeline architecture in this paper. Based on Xilinx xcvu13p-flga2577-1-e field programmable gate array (FPGA) chips, we develop a successive cancellation list (CRC-SCL) decoder based on cyclic redundancy check codes with a code length of 256 for the first time in hardware, and this decoder can be adapted to various code rates. The total throughput of the decoder reaches 40 Gbit/s at the maximum clock frequency of 156.25 MHz. In addition, we carry out 56-Gbit/s (28-Gbaud) QPSK back-to-back experiments based on polar codes. Experimental results show that the CRC-SCL decoder implemented in this paper can obtain a coding gain of 7.5 dB when the bit error rate is equal to 10 ^-3. Furthermore, to balance the error correction performance and resource consumption, we also analyze the influence of quantization bits on the decoder performance.