[1] P A Meinerzhagen, C Tokunaga, A Malavasi et al. An energy-efficient graphics processor in 14-nm tri-gate CMOS featuring integrated voltage regulators for fine-grain DVFS, retentive sleep, and
[2]
[3] S Chong, P K Chan. A 0.9-
[4] Y Lu, Y P Wang, Q Pan et al. A fully-integrated low-dropout regulator with full-spectrum power supply rejection. IEEE Trans Circuits Syst I, 62, 707(2015).
[5] M Huang, H G Feng, Y Lu. A fully integrated FVF-based low-dropout regulator with wide load capacitance and current ranges. IEEE Trans Power Electron, 34, 11880(2019).
[6]
[7] C J Park, M Onabajo, J Silva-Martinez. External capacitor-less low drop-out regulator with 25 dB superior power supply rejection in the 0.4–4 MHz range. IEEE J Solid-State Circuits, 49, 486(2014).
[8] Y Lu, R P Martins, U Seng-Pan et al. A 312 ps response-time LDO with enhanced super source follower in 28 nm CMOS. Electron Lett, 52, 1368(2016).
[9] V Gupta, G A Rincon-Mora, P Raha. Analysis and design of monolithic, high PSR, linear regulators for SoC applications. IEEE International SOC Conference, 311(2004).
[10] Y Okuma, K Ishida, Y Ryu et al. 0.5-V input digital LDO with 98.7% current efficiency and 2.7-
[11] M Huang, Y Lu, S W Sin et al. Limit cycle oscillation reduction for digital low dropout regulators. IEEE Trans Circuits Syst II, 63, 903(2016).
[12]
[13] M Huang, Y Lu, S W Sin et al. A fully integrated digital LDO with coarse-fine-tuning and burst-mode operation. IEEE Trans Circuits Syst II, 63, 683(2016).
[14] L G Salem, J Warchall, P P Mercier. A successive approximation recursive digital low-dropout voltage regulator with PD compensation and sub-LSB duty control. IEEE J Solid-State Circuits, 53, 35(2018).
[15]
[16] M Huang, Y Lu, S P U et al. An analog-assisted tri-loop digital low-dropout regulator. IEEE J Solid-State Circuits, 53, 20(2018).
[17] M Huang, Y Lu, X Lu. Partial analogue-assisted digital low dropout regulator with transient body-drive and 2.5 × FOM improvement. Electron Lett, 54, 282(2018).
[18]
[19] M A Akram, W Hong, I C Hwang. Fast transient fully standard-cell-based all digital low-dropout regulator with 99.97% current efficiency. IEEE Trans Power Electron, 33, 8011(2018).
[20]
[21]
[22]
[23]
[24] S Gangopadhyay, D Somasekhar, J W Tschanz et al. A 32 nm embedded, fully-digital, phase-locked low dropout regulator for fine grained power management in digital circuits. IEEE J Solid-State Circuits, 49, 2684(2014).
[25] S Kundu, M Q Liu, S J Wen et al. A fully integrated digital LDO with built-in adaptive sampling and active voltage positioning using a beat-frequency quantizer. IEEE J Solid-State Circuits, 54, 109(2019).
[26] Y H Lee, S Y Peng, C C Chiu et al. A low quiescent current asynchronous digital-LDO with PLL-modulated fast-DVS power management in 40 nm SoC for MIPS performance improvement. IEEE J Solid-State Circuits, 48, 1018(2013).
[27] F Yang, P K T Mok. A nanosecond-transient fine-grained digital LDO with multi-step switching scheme and asynchronous adaptive pipeline control. IEEE J Solid-State Circuits, 52, 2463(2017).
[28]
[29]
[30] Y N Zhang, H X Song, R R Zhou et al. A capacitor-less ripple-less hybrid LDO with exponential ratio array and 4000x load current range. IEEE Trans Circuits Syst II, 66, 36(2019).
[31] X Y Wang, P P Mercier. A dynamically high-impedance charge-pump-based LDO with digital-LDO-like properties achieving a sub-4-fs FoM. IEEE J Solid-State Circuits, 55, 719(2020).
[32] S B Nasir, S Sen, A Raychowdhury. Switched-mode-control based hybrid LDO for fine-grain power management of digital load circuits. IEEE J Solid-State Circuits, 53, 569(2018).
[33]
[34]
[35] M Huang, Y Lu, R P Martins. An analog-proportional digital-integral multiloop digital LDO with PSR improvement and LCO reduction. IEEE J Solid-State Circuits, 55, 1637(2020).
[36]
[37] Y F Li, X Y Zhang, Z Zhang et al. A 0.45-to-1.2-V fully digital low-dropout voltage regulator with fast-transient controller for near/subthreshold circuits. IEEE Trans Power Electron, 31, 6341(2016).
[38]
[39] A Singh, M Kar, V C K Chekuri et al. A digital low-dropout regulator with autotuned PID compensator and dynamic gain control for improved transient performance under process variations and aging. IEEE Trans Power Electron, 35, 3242(2020).
[40] K Z Ahmed, H K Krishnamurthy, C Augustine et al. A variation-adaptive integrated computational digital LDO in 22-nm CMOS with fast transient response. IEEE J Solid-State Circuits, 55, 977(2020).
[41]
[42] B Hershberg, S Weaver, K Sobue et al. Ring amplifiers for switched capacitor circuits. IEEE J Solid-State Circuits, 47, 2928(2012).
[43]
[44]
[45] P Hazucha, T Karnik, B A Bloechel et al. Area-efficient linear regulator with ultra-fast load regulation. IEEE J Solid-State Circuits, 40, 933(2005).
[46] Q H Duong, H H Nguyen, J W Kong et al. Multiple-loop design technique for high-performance low-dropout regulator. IEEE J Solid-State Circuits, 52, 2533(2017).