Zhan-Gang Zhang, Zhi-Feng Lei, Teng Tong, Xiao-Hui Li, Song-Lin Wang, Tian-Jiao Liang, Kai Xi, Chao Peng, Yu-Juan He, Yun Huang, Yun-Fei En. Comparison of neutron induced single event upsets in 14 nm FinFET and 65 nm planar static random access memory devices [J]. Acta Physica Sinica, 2020, 69(5): 056101-1
- Acta Physica Sinica
- Vol. 69, Issue 5, 056101-1 (2020)
Fig. 1. Experimental setup (neutron beam channel is loca-ted behind the test board, and aligned with the device under test).
Fig. 2. Neutron energy spectrum of the experimental terminal.
Fig. 3. Comparison of neutron (E > 10 MeV) SEU cross section of 65 nm planar and 14 nm FinFET SRAM devices.
Fig. 4. Comparison of thermal neutron SEU cross section of 65 nm planar and 14 nm FinFET SRAM devices.
Fig. 5. Relationship between LET value and energy of (a) Li ion and (b) He ion in silicon material.
Fig. 6. Heavy ion experiment results of 14 nm FinFET SRAM.
Fig. 7. Comparison of neutron MBU ratio of 65 nm planar and 14 nm FinFET SRAM devices (using the full spectrum in Fig. 2 ).
Fig. 8. Reverse analysis of 14 nm FinFET SRAM: (a) Cross section; (b) memory area image.
Fig. 9. Reverse analysis of 65 nm SRAM: (a) Cross section; (b) memory area image.
Fig. 10. 14 MeV and 1600 MeV neutron induced secondary particle distribution in the device SV (W material in the device model is replaced by silica).
Fig. 11. 14 MeV and 1600 MeV neutron induced secondary particle distribution in the device SV (real device model).
Fig. 12. The LET value and range of secondary particles generated by 14 MeV and 1600 MeV neutrons in the device SV.
Fig. 13. The deposition charge of 14 MeV and 1600 MeV neutrons in the device SV.
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Table 1.
Parameters of devices under test.
被测器件参数
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Table 2.
Memory cell size and SV parameters for the 14 nm FinFET SRAM and 65 nm SRAM devices.
14 nm FinFET SRAM和65 nm SRAM的存储单元尺寸和灵敏区参数
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