The demand for high-performance, compact, and battery-operated devices for RF applications leads to the need for technology where power losses should be low^[1]. To reduce the losses associated with the RF power devices, silicon material needs to be replaced by the other semiconductor material because the devices based on this technology are reaching their theoretical limits^[2]. To compensate for several limitations found in Si-based devices, wide bandgap (WBG) semiconductors like GaN (~3.4 eV) and SiC (~3.3 eV) became the favorable materials to be opted^[3]. In high power applications, the devices based on WBG (i.e GaN & SiC) semiconductor materials show the excellent capability of withstanding high breakdown voltage ( V_br) with reduced power losses and leakages in comparison to Si^[4]. However, for efficient implementation of high-power RF amplifiers with stable high-temperature operation certain parameters such as R_ON, off-state leakage current, switching speed, and V_br, need to be optimized^[5].

As a power electronics semiconductor, β-Ga₂O₃ has emerged in several fields from very high voltage power switching^[5-7] to even GHz RF power amplification^[8]. This is due to the advantage of high theoretical critical field strength (E_c) that surpasses both the SiC and GaN E_c values^[9]. The two important high-frequency power device figure-of-merits (FOMs); i.e., the Johnson (2844.4) and Baliga’s (3214.1) FOMs are found to be exceptionally high for Ga₂O₃ concerning silicon^[10]. With its mobility ranging as 100 cm²/(V·s), β-Ga₂O₃ transistors trend an opportunity towards operating as amplifiers that can be used for RF applications; i.e., RF amplifiers, RF switches and many more^{[5, 8]}.

In RF and power electronic applications based on gallium oxide MOS technology, several types of research have been carried out^[3-10]. Mastro et al. discloses the reference to further opportunities in space of Ga₂O₃ and formulated a study that depicts Ga₂O₃ possess high electron saturation velocity (v_sat) along with high output current density, which gives a high value of cut-off frequency^[10]. Further, Higashiwaki et al. demonstrates the performance of gallium oxide MOSFET under depletion mode operating condition and observed that 2 μm of gate length MOS device result in minimum off-state leakage current with I_ON/I_OFF ratio greater than 10^10[4]. Green et al. diverted the further study of gallium oxide MOSFET towards RF performance and stated its high value of g_m (21 mS/mm) and f_T (3.3 GHz)^[8].

As 2D material technologies emerge in the space for future electronic devices, black phosphorous (BP) and also graphene have become rewarding materials. Recently, due to excellent electron transport properties, graphene has been the main focus for future RF electronics^[11]. Being considered as a gapless semiconductor, graphene has an advantage of higher carrier mobility even at room temperature, which adds that β-Ga₂O₃ quite compatible with it. However, due to its poor saturation behavior, the use of graphene in RF and switching applications is still limited.

BP has been considered as another tunable bandgap material^[12] with its higher carrier mobility stated as 1000 cm²/(V·s). Due to the improved saturation behavior property, BP is particularly suited as an alternative for graphene^{[11, 13]}. Li et al. fabricated FET based upon BP crystals with thickness referring to few nanometers. Reliability in these devices was observed at room temperature with 7.5 nm thickness and drain current modulation of 10⁵ results in a better I–V characteristic^[14]. Yan et al. studied the performance of β-Ga₂O₃/graphene heterostructure in a vertical barristor. The fabricated structure results in a high breakdown field of ~5 MV/cm and was found to be close to the theoretical E_c of β-Ga₂O₃ (~8 MV/cm)^[15]. A comprehensive study for analog and RF performance of BP (20 nm) based MOSFET was analyzed by Kumar et al.^[16]. The figure of merits investigated was –f_T, f_max, stern stability factor, various power gains along with parasitic capacitances at THz frequency range. The results show that the designed device is more suitable for RF applications. Yadava and Chauhan insights the introduction of a single layer of graphene/BP in Ga₂O₃ MOSFET to improve its RF performance. The losses associated with the introduction of the BP layer in Ga₂O₃ MOSFET has not been discussed in the above work^[17]. But the problem lied in the β-Ga₂O₃ doping profile as the lack of p-type doping on β-Ga₂O₃ limits certain operations. Usually, for growing β-Ga₂O₃ single crystals and thin films, n-type was considered because their existence of unmeant impurities^[18].

To overcome the lack of p-type conductivity in Ga₂O₃, p-type oxide (like Ir₂O₃, NiO) based heterostructures were considered^[19]. Usage of the MOSFET with p-type Ir₂O₃ oxide-based channel region was demonstrated by FLOSFIA Inc.^[20], which is considered as a groundbreaking work for future high-power electronics devices. Kokunan et al. fabricated the NiO/Ga₂O₃ hetero-junction diode by growing the p-type NiO layer on the Ga₂O₃ substrate using the sol-gel technique. The fabricated devices showed good rectifying behavior with a ratio >10 ⁸ at ± 3.0 V^[21]. The RF performance investigation of NiO (p-type) pocket based Ga₂O₃ MOSFET was done by Yadava and Chauhan, where the capacitance C_gs, which has a direct correlation with the device leakage, decreases with the use of NiO pocket region at both of the channel interfaces^[22].

This paper investigates the impact of the BP layer on the RF performance of NiO pocket based gallium oxide MOSFET. The key FOMs for device performance evaluation includes the transconductance (g_m), gate dependent intrinsic-capacitances (C_gd and C_gs), cutoff frequency (f_T), gain bandwidth (GBW) product and output-conductance (g_d). Similarly, power-gain (G_p), power added efficiency (PAE), and output power (P_OUT) are also investigated for large-signal continuous-wave (CW) RF performance evaluation.

The structures of p-type NiO-pocket based β-Ga₂O₃ and p-type NiO-pocket based β-Ga₂O₃/black phosphorous heterostructure MOSFETs are shown in Figs. 1(a) and 1(b), respectively. Figs. 2(a) and 2(b) depicts the lattice temperature of conventional and p-type NiO-pocket based MOSFETs obtained at V_DS = + 40 V and V_GS = + 4 V. In β-Ga₂O₃ MOSFET shown in Fig 2(a), the maximum value of lattice temperature reaches to ~ 422 °C. However, with the use of p-type NiO-pocket in the device and under the similar device operating conditions, it only reaches 400 °C. Similarly, Figs. 3(a) and 3(b) shows the potential distribution of conventional and p-type NiO-pocket based MOSFETs respectively. In Fig. 3(b), the use of p-type NiO-pocket at both the channel interfaces results in a minute decrease in the potential is observed. This decrease is due to the abrupt transition in the device impurity doping profile from Ga₂O₃ (n-type) channel to NiO-pocket (p-type) regions. In the device, a 300 nm thick n-type β-Ga₂O₃ channel region was made to grow on a single crystal of β-Ga₂O₃ substrate. The n-type impurity doping concentration of the channel region is ~7 × 10¹⁷ cm^–3 and around half of this is assumed to be activated by considering the measured C–V data of the fabricated gallium oxide MOS device^[4]. The formation of source and drain electrodes is carried out by utilizing multiple Si⁺ implants with a 150 nm deep box profile of n-type having a doping concentration of 3 × 10¹⁹ cm^–3 optimized from the collective data of the device^[4].

The overall distance between the source and drain region was 20 µm. On the top of the channel region, a 20 nm thick Al₂O₃ layer was made to deposited as a gate dielectric layer accompanied by the deposition of 2 µm long Ti/Pt/Au metal gate on the top. In NiO-pocket based β-Ga₂O₃/BP heterostructure MOSFET, a BP layer of 10 nm thick was made to deposited over the substrate, while keeping other conditions similar. The important material parameters used in the design of the β-Ga₂O₃/BP heterostructure MOS device are summarized in Table 1.

All the parameters and RF FOMs are extracted out from the ATLAS device simulation tool^[23]. The Newton numerical technique is used to obtain numerical solutions because it provides better convergence. For obtaining in the device LAT.TEMP parameter is set up in the model parameter. Using equation (1), we can attain temperature-dependent electron mobility with lattice temperature coefficient TMUN = 2^[23]. Along with the ATLAS simulation tool, ATHENA (process simulator) is also used to pro-create multiple Si⁺ implantations^[4] using a material implant model called BCA.

$ {{{\mu}} }_{{\rm{n}}0}={\rm{MUN}}{\left(\frac{{T}_{\rm{L}}}{300}\right)}^{-\rm{TMUN}}, $  (1)

where μ_n0 is low field mobility, MUN is the electron mobility and T_L is lattice temperature.

In the material parameters of the BP region (see Table 1), the bandgap (E_g) is set to 1.88 eV, the relative permittivity and electron affinity of 6.1 and 5.5 eV are taken, respectively. These parameters are obtained from the experimental measurement of the BP FET given by Li et al.^[14].

The fabrication of the gallium oxide MOSFET was already demonstrated by Higashiwaki et al.^[4] and Zing et al.^[24]. In the initial fabrication step, a single-crystal of the β-Ga₂O₃ substrate is made to doped with Fe, over which an Sn doped 300 nm thick n-Ga₂O₃ channel layer was formed by using the MBE technique^[4]. Using Knudsen cells, Sn and Ga fluxes are carried out by powdered SnO₂ and Ga metal, respectively. Followed by growing of the SiO₂ layer using PECVD^{[4, 6]}. To open up, source, and drain regions, lithography is being performed. Generally, to carry out these fabrication steps, often positive PR along with maskless lithography is used^[25]. Using multiple Si⁺ implantations, source, and drain electrode regions are defined accompanied by annealing^[25]. Thereafter, two NiO pocket regions of 10 nm thicker in length were made to form at the channel (drain/channel & source/channel) interfaces. Now, the grown NiO region is made p-type (impurity concentration ~1.6 × 10 ¹⁷ cm^–3) by adding Li as an acceptor impurity^[21]. After this, the removal of the deposited SiO₂ on the gate region was done by using RIE^[4]. Now, the ALD technique is utilization for the deposition of Al₂O₃ of 20 nm thick as a gate dielectric layer followed by RIE^{[25, 26]}. Soon after the fourth lithography, a 2 µm long Ti/Pt/Au metal gate is formed over the top of the gate oxide layer^{[4, 25]}. For both Ga₂O₃/BP and p-type NiO pocket based β-Ga₂O₃/BP heterostructure MOSFETs, a process step is maintained soon after Ga₂O₃ substrate formation. For this process step, the PDMS stamping technique is used to deposit a thin layer of BP over the substrate layer followed by epitaxial growth of the channel region^{[16, 17]}.

To examine RF performance of the devices, the FOMs such as transconductance (g_m) gate dependent intrinsic-capacitances (C_gd and C_gs), cutoff frequency (f_T), gain bandwidth (GBW) product and output-conductance (g_d) are used. All of the analysis is done by using ATLAS 2D simulator^[23].

Fig. 4 shows the DC transfer characteristics of simulated devices, to consider the effect of NiO pocket on β-Ga₂O₃ MOSFET with the BP layer. The transfer and the output characteristics of the devices are shown in Figs. 4 and 5, respectively, in which the conventional device is taken from the reported literature and is very much in agreement with the experimental device demonstrated by Higashiwaki et al.^[4].

In Fig. 4, the increased carrier to carrier scattering at the channel interfaces results in a small increase in the value of drain current (I_D) in p-type NiO pocket based Ga₂O₃ (NiO-GO)^[22] MOSFET in comparison to the Conventional Ga₂O₃ MOSFET (Conv. GO)^[17], experimental Ga₂O₃ MOSFET (Exp.)^[4] and β-Ga₂O₃/BP (GO/BP) heterostructure MOSFET. For the devices, the value of the I_on/I_off ratio of about 1 × 10¹⁰ is observed with off-state leakage in the range of a few pA.

Fig. 6 shows the output conductance characteristics of the device plotted between g_d and V_DS with V_GS = –4 V. For high gain applications, a device should possess a lower value of g_d which can be seen in p-type NiO β-Ga₂O₃/BP (NiO-GO/BP) heterostructure MOSFET. For a device to be used for RF applications, higher output gain requires lower output conductance as depicted in Eq. (3).

By performing small-signal AC analysis after the post-processing operation of DC results, one can obtain the device C_gd and C_gs values at the constant frequency of 0.8 GHz using DC gate voltage swept from –25 to 4 V. Figs. 7 and 8 represent the variation in C_gd and C_gs for different V_GS values, respectively. The increased capacitive coupling between the gate and drain terminals of the NiO-GO^[22] and NiO-GO/BP MOSFETs results in larger C_gd value in comparison with Conv. GO MOSFET^[17]. However, the C_gs value which straightly contributes to the leakage is found to be 0.7 times lesser for NiO-GO/BP MOSFET on comparing to NiO-GO^[22] MOSFET.

$ {g}_{\rm{m}}=\frac{\partial {I}_{\rm{D}}}{\partial {V}_{\rm{GS}}}, $  (2)

$ {g}_{\rm{d}}=\frac{\partial {I}_{\rm{D}}}{\partial {V}_{\rm{DS}}}, $  (3)

$ {f}_{\rm{T}}\approx \frac{{g}_{\rm{m}}}{2{{\pi }}({C}_{\rm{gs}}+{C}_{\rm{gd}})}, $  (4)

$ {\rm{GBW}} =\frac{{g}_{\rm{m}}}{2\pi \times 10\times {C}_{\rm{gd}}}, $  (5)

$ {f}_{\rm{T}}={f}_{0}\cdot\left|{H}_{21}\right|. $  (6)

The f_T (see Eq. (4)) is the key FOMs for the depiction of the high-frequency performance of RF devices. The cutoff frequency also stated as GBW (see Eq. (5)) is simultaneously related to H₂₁ (short-circuit current gain). Regarding the two-port network, H₂₁ is known as the ratio of output terminal current to the input terminal current of small-signal with output short-circuited. This parameter is frequency-dependent and its magnitude sweeps at high frequencies with a slope of –20 dB/dec. Keeping this justification, f_T can be termed as the frequency value at which the magnitude of H₂₁ decreases to unity. Using Eq. (6) we can evaluate the f_T and inset of Fig. 7 shows the f_T curve of the proposed device. A smaller value of f_T is observed in the case of NiO-GO^[22] and NiO-GO/BP MOSFETs in comparison to the Con. GO^[17]. However, a 1.09 times improvement in the value of f_T is found in NiO-GO/BP MOSFET in comparison to NiO-GO^[22] MOSFET.

In Fig. 8, the inset graph indicates that the GBW product decreases with the use of the NiO pocket region of p-type in the device. This is due to the decreased value of g_m. However, to compensate for this, a thin BP layer is used below the channel region which improves GBW product in comparison to NiO-GO^[22] MOSFET.

In large-signal RF applications, P_OUT, PAE, and G_P are analyzed. Fig. 9 (see Figs. 9(a) and 9(b)) represent the plot of P_OUT, G_P, and PAE versus P_IN at V_DS and V_GS of 25 and –4 V, respectively. For any MOSFET based power amplifiers, efficiency (η) can be estimated out as (see Eq. (7)):

$\eta = \frac{{{{{P}}_{{\rm{Load}}}}}}{{{{{P}}_{{\rm{Supply}}}}}},$ (7)

where P_Load is the average power delivered to load terminal and P_Supply is average supply power. In the power amplifiers, where heat dissipation is of major concern, PAE (see Eq. (8)) is used as an important FOM.

${\rm{PAE}} = \frac{{{{{P}}_{{\rm{Load}}}} - {{{P}}_{{\rm{Input}}}}}}{{{{{P}}_{{\rm{Supply}}}}}},$ (8)

where P_Input is the average input power.

In the NiO-GO/BP MOSFET based PA circuit, due to the increased feedback (which increases the value of C_gd as stated above), the value of both PAE & G_P decreases (see Fig. 9(b)). However, these large-signal RF FOMs are found to be improved on comparing it with NiO-GO^[22] MOSFET, which is depicted because there is an introduction of the BP layer underneath the channel region. For GO/BP MOSFET, the measured G_P is 13.02 dB and is 3.27 dB superior to NiO-GO^[22] MOSFET. Nevertheless, the value of PAE measured is 2.03% less efficient to NiO-GO^[22] MOSFET. Also, we can see from Table 2 that NiO-GO/BP MOSFET shows better RF performance with improved power gain and low leakages.

The p-type NiO pocket in Ga₂O₃/black phosphorous heterostructure MOSFET is used to improve the device performance by reducing the leakages and other associated losses. The FOMs that are used in this analysis to investigate its applicability in the RF applications are f_T, g_m, g_d, and the intrinsic capacitances (C_gd and C_gs) and large-signal RF FOMs like P_OUT, G_p, and PAE. The I_on/I_off of about 1 × 10¹⁰ is observed with off-state leakage in the range of a few pA. The C_gs value which straightly contributes to the leakage is found to be 0.7 times lesser for NiO-GO/BP MOSFET along with 1.09 times improvement in f_T in comparison to that of NiO-GO^[22] MOSFET. In the NiO-GO/BP MOSFET based PA circuit, due to the increased feedback (which increases the value of C_gd as stated above), the value of both PAE & G_P decreases. However, these large-signal RF FOMs are found to be improved on comparison with NiO-GO^[22] MOSFET and this is depicted because there is an introduction of the BP layer underneath the channel region. For GO/BP MOSFET, the measured G_P is 13.02 and is 3.27 dB superior to NiO-GO^[22] MOSFET. Nevertheless, the value of PAE measured is 2.03% less efficient to NiO-GO^[22] MOSFET. The obtained results show that the NiO-GO/BP MOSFET has better RF performance with improved power gain and low leakages. The RF performance of the proposed device can be improved with the development of p-type material for Ga₂O₃ semiconductor-based devices.