16-channel photonic–electric co-designed silicon transmitter with ultra-low power consumption

Jingbo Shi; Ming Jin; Tao Yang; Haowen Shu; Fenghe Yang; Han Liu; Yuansheng Tao; Jiangrui Deng; Ruixuan Chen; Changhao Han; Nan Qi; Xingjun Wang

doi:10.1364/PRJ.469556

Journals >Photonics Research >Volume 11 >Issue 2 >Page 143 > Article

Photonics Research
Vol. 11, Issue 2, 143 (2023)

16-channel photonic–electric co-designed silicon transmitter with ultra-low power consumption

Jingbo Shi^{1、7、†,*}, Ming Jin^1、†, Tao Yang², Haowen Shu¹, Fenghe Yang³, Han Liu⁴, Yuansheng Tao¹, Jiangrui Deng¹, Ruixuan Chen¹, Changhao Han¹, Nan Qi^{4、5、8、*}, and Xingjun Wang^{1、6、9、*}

Author Affiliations

¹State Key Laboratory of Advanced Optical Communication Systems and Networks, School of Electronics, Peking University, Beijing 100871, China

²College of Engineering, Peking University, Beijing 100871, China

³Peking University Yangtze Delta Institute of Optoelectronics, Nantong 226010, China

⁴State Key Laboratory of Superlattices and Microstructures, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

⁵Center of Material Science and Optoelectronics Engineering, University of Chinese Academy of Sciences, Beijing 100049, China

⁶Frontier Science Center for Nano-optoelectronics, Peking University, Beijing 100871, China

⁷e-mail: jingboshi@pku.edu.cn

⁸e-mail: qinan@semi.ac.cn

⁹e-mail: xjwang@pku.edu.cn

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DOI: 10.1364/PRJ.469556 Cite this Article Set citation alerts

Jingbo Shi, Ming Jin, Tao Yang, Haowen Shu, Fenghe Yang, Han Liu, Yuansheng Tao, Jiangrui Deng, Ruixuan Chen, Changhao Han, Nan Qi, Xingjun Wang. 16-channel photonic–electric co-designed silicon transmitter with ultra-low power consumption[J]. Photonics Research, 2023, 11(2): 143 Copy Citation Text

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Fig. 1. Proposed SiPh transmitter: (a) hybrid integration; (b) 16-CH MZM; and (c) 8-CH CMOS driver.

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Fig. 2. (a) Cross section structure of the SiPh modulator arms. (b) EO bandwidth of the modulator.

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Fig. 3. Proposed distributed CMOS driver: (a) driver architecture; (b) two-tap FFE; and (c) push–pull driver cell.

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Fig. 4. Measured frequency response of proposed driver: (a) S11; (b) S22; and (c) S21.

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Fig. 5. Measured electrical eye diagrams: (a) 32 Gb/s, FFE disabled; (b) 32 Gb/s, FFE enabled; (c) 50 Gb/s, Channel 1; (d) 50 Gb/s, Channel 3; (e) 50 Gb/s, Channel 5; and (f) 50 Gb/s, Channel 7.

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Fig. 6. Experimental setup of the optical characterization. EDFA, erbium-doped fiber amplifier; and PRBS, pseudorandom binary sequence.

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Fig. 7. Measured optical eye diagrams: (a) 32 Gb/s, FFE disabled; (b) 32 Gb/s, FFE enabled; (c) 50 Gb/s, Channel 1; (d) 50 Gb/s, Channel 3; (e) 50 Gb/s, Channel 5; and (f) 50 Gb/s, Channel 7.

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Transmitter Platform	Laser Band	Signal Pattern	Channel Number	Swing ( $V_{PP}$ )	Data Rate (Gb/s)	EIC Process	Power (mW)	Efficiency (pJ/bit)
SiPh MRM [26]	O	PAM4	1	3.0	112	28 nm CMOS	676^a	6.0
SiPh MZM [37]	O	PAM4	4	–	53.15	55 nm BiCMOS	290	5.46
SiPh MZM [38]	O	NRZ	1	2.5	25	65 nm CMOS	275	11.0
SiPh MZM [39]	O	PAM4	1	–	56	55 nm BiCMOS	300	5.36
SiPh MZM [40]	O	NRZ/PAM4	2	4.0	56	130 nm BiCMOS	593	10.6
SiPh MZM [41]	–	NRZ/PAM4	1	1.8	56	16 nm CMOS	708	12.6
SiPh MZM [27]	C	PAM4	4	–	200	–	–	–
SiPh MZM [28]	C	PAM4	2	4.0	50	40 nm CMOS	1340^b	26.8
SiPh MZM [29]	C	NRZ	1	–	100	28 nm CMOS	203	2.03
SiPh MZM (This work)	C	NRZ	16	4.0	50	65 nm CMOS	267.6	5.35