An integrated front-end vertical CMOS Hall magnetic sensor is proposed for the in-plane magnetic field measurement. To improve the magnetic sensitivity and to obtain low offset, a fully symmetric vertical Hall device (FSVHD) has been optimized with a minimum size design. A new four-phase spinning current modulation associated with a correlated double sampling (CDS) demodulation technique has been further applied to compensate for the offset and also to provide a linear Hall output voltage. The vertical Hall sensor chip has been manufactured in a 0.18 μm low-voltage CMOS technology and it occupies an area of 1.54 mm². The experimental results show in the magnetic field range from –200 to 200 mT, the entire vertical Hall sensor performs with the linearity of 99.9% and the system magnetic sensitivity of 1.22 V/T and the residual offset of 60 μT. Meanwhile, it consumes 4.5 mW at a 3.3 V supply voltage. The proposed vertical Hall sensor is very suitable for the low-cost system-on-chip (SOC) implementation of 2D or 3D magnetic microsystems.