[1] W W Shan, M H Yang, J M Xu et al. A 510nW 0.41V low-memory low-computation keyword-spotting chip using serial FFT-based MFCC and binarized depthwise separable convolutional neural network in 28nm CMOS. 2020 IEEE International Solid-State Circuits Conference, 230(2020).

[2] D W Wang, S J Kim, M H Yang et al. A background-noise and process-variation-tolerant 109nW acoustic feature extractor based on spike-domain divisive-energy normalization for an always-on keyword spotting device. 2021 IEEE International Solid-State Circuits Conference, 64, 160(2021).

[3] T Tambe, E Y Yang, G G Ko et al. A 25mm2 SoC for IoT devices with 18ms noise-robust speech-to-text latency via Bayesian speech denoising and attention-based sequence-to-sequence DNN speech recognition in 16nm FinFET. 2021 IEEE International Solid-State Circuits Conference, 64, 158(2021).

[4] M Cho, S Oh, Z Shi et al. A 142nW voice and acoustic activity detection chip for mm-scale sensor nodes using time-interleaved mixer-based frequency scanning. 2019 IEEE International Solid-State Circuits Conference, 278(2019).

[5] F F Chen, K F Un, W H Yu et al. A 108nW 0.8mm2 analog voice activity detector (VAD) featuring a time-domain CNN as a programmable feature extractor and a sparsity-aware computational scheme in 28nm CMOS. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[6] Y C Lu, V L le, T T H Kim. A 184µW real-time hand-gesture recognition system with hybrid tiny classifiers for smart wearable devices. 2021 IEEE International Solid-State Circuits Conference, 64, 156(2021).

[7] D Im, G Park, Z Y Li et al. DSPU: A 281.6mW real-time depth signal processing unit for deep learning-based dense RGB-D data acquisition with depth fusion and 3D bounding box extraction in mobile platforms. 2022 IEEE International Solid-State Circuits Conference, 33.4(2022).

[8] Z Yuan, Y X Yang, J S Yue et al. A 65nm 24.7µJ/frame 12.3mW activation-similarity-aware convolutional neural network video processor using hybrid precision, inter-frame data reuse and mixed-bit-width difference-frame data codec. 2020 IEEE International Solid-State Circuits Conference, 232(2020).

[9] Y Wang, Y B Qin, D Z Deng et al. A 28nm 27.5TOPS/W approximate-computing-based transformer processor with asymptotic sparsity speculating and out-of-order computing. 2022 IEEE International Solid-State Circuits Conference, 29.2(2022).

[10] F B Tu, Z H Wu, Y Q Wang et al. A 28nm 15.59µJ/token full-digital bitline-transpose CIM-based sparse transformer accelerator with pipeline/parallel reconfigurable modes. 2022 IEEE International Solid-State Circuits Conference, 29.3(2022).

[11] R Eki, S Yamada, H Ozawa et al. A 1/2.3inch 12.3Mpixel with on-chip 4.97TOPS/W CNN processor back-illuminated stacked CMOS image sensor. 2021 IEEE International Solid-State Circuits Conference, 9.6(2021).

[12] D M Niu, S C Li, Y H Wang et al. 184QPS/W 64Mb/mm2 3D logic-to-DRAM hybrid bonding with process-near-memory engine for recommendation system. 2022 IEEE International Solid-State Circuits Conference, 29.1(2022).

[13] X Si, Y N Tu, W H Huang et al. A 28nm 64Kb 6T SRAM computing-in-memory macro with 8b MAC operation for AI edge chips. 2020 IEEE International Solid-State Circuits Conference, 246(2020).

[14] J S Yue, Z Yuan, X Y Feng et al. A 65nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter/intra-macro data reuse. 2020 IEEE International Solid-State Circuits Conference, 234(2020).

[15] J S Yue, X Y Feng, Y F He et al. A 2.75-to-75.9 TOPS/W computing-in-memory NN processor supporting set-associate block-wise zero skipping and Ping-pong CIM with simultaneous computation and weight updating. 2021 IEEE International Solid-State Circuits Conference, 238(2021).

[16] Y D Chih, P H Lee, H Fujiwara et al. An 89TOPS/W and 16.3 TOPS/mm2 all-digital SRAM-based full-precision compute-in memory macro in 22nm for machine-learning edge applications. 2021 IEEE International Solid-State Circuits Conference, 64, 252(2021).

[17] B N Yan, J L Hsu, P C Yu et al. A 1.041-Mb/mm2 27.38-TOPS/W signed-INT8 dynamic-logic-based ADC-less SRAM compute-in-memory macro in 28nm with reconfigurable bitwise operation for AI and embedded applications. 2022 IEEE International Solid-State Circuits Conference, 188(2022).

[18] P C Wu, J W Su, Y L Chung et al. A 28nm 1Mb time-domain computing-in-memory 6T-SRAM macro with a 6.6ns latency, 1241GOPS and 37.01 TOPS/W for 8 b-MAC operations for edge-AI devices. 2022 IEEE International Solid-State Circuits Conference, 190(2022).

[19] J M Hung, Y H Huang, S P Huang et al. An 8-Mb DC-current-free binary-to-8b precision ReRAM nonvolatile computing-in-memory macro using time-space-readout with 1286.4 TOPS/W-21.6 TOPS/W for edge-AI devices. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[20] H Fujiwara, H Mori, W C Zhao et al. A 5-nm 254-TOPS/W 221-TOPS/mm2 fully-digital computing-in-memory macro supporting wide-range dynamic-voltage-frequency scaling and simultaneous MAC and write operations. 2022 IEEE International Solid-State Circuits Conference, 186(2022).

[21] D W Wang, C T Lin, G K Chen et al. DIMC: 2219TOPS/W 2569F2/b digital in-memory computing macro in 28nm based on approximate arithmetic hardware. 2022 IEEE International Solid-State Circuits Conference, 266(2022).

[22] J W Su, Y C Chou, R H Liu et al. A 28nm 384kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips. 2021 IEEE International Solid-State Circuits Conference, 250(2021).

[23] H Y Jia, M Ozatay, Y Q Tang et al. A programmable neural-network inference accelerator based on scalable in-memory computing. 2021 IEEE International Solid-State Circuits Conference, 236(2021).

[24] J W Su, X Si, Y C Chou et al. A 28nm 64Kb inference-training two-way transpose multibit 6T SRAM compute-in-memory macro for AI edge chips. 2020 IEEE International Solid-State Circuits Conference, 240(2020).

[25] K Ueyoshi, I A Papistas, P Houshmand et al. DIANA: an end-to-end energy-efficient digital and ANAlog hybrid neural network SoC. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[26] R Q Guo, Z H Yue, X Si et al. A 5.99-to-691.1 TOPS/W tensor-train in-memory-computing processor using bit-level-sparsity-based optimization and variable-precision quantization. 2021 IEEE International Solid-State Circuits Conference, 242(2021).

[27] F B Tu, Y Q Wang, Z H Wu et al. A 28nm 29.2TFLOPS/W BF16 and 36.5TOPS/W INT8 reconfigurable digital CIM processor with unified FP/INT pipeline and bitwise in-memory booth multiplication for cloud deep learning acceleration. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[28] S S Xie, C Ni, A Sayal et al. eDRAM-CIM: Compute-in-memory design with reconfigurable embedded-dynamic-memory array realizing adaptive data converters and charge-domain computing. 2021 IEEE International Solid-State Circuits Conference, 248(2021).

[29] S Lee, K Kim, S Oh et al. A 1nm 1.25V 8Gb, 16Gb/s/pin GDDR6-based accelerator-in-memory supporting 1TFLOPS MAC operation and various activation functions for deep-learning applications. 2022 IEEE International Solid-State Circuits Conference, 178(2022).

[30] Z Y Chen, X Chen, J Gu. A 65nm 3T dynamic analog RAM-based computing-in-memory macro and CNN accelerator with retention enhancement, adaptive analog sparsity and 44 TOPS/W system energy efficiency. 2021 IEEE International Solid-State Circuits Conference, 240(2021).

[31] C X Xue, T Y Huang, J S Liu et al. A 22nm 2Mb ReRAM compute-in-memory macro with 121-28 TOPS/W for multibit MAC computing for tiny AI edge devices. 2020 IEEE International Solid-State Circuits Conference, 244(2020).

[32] C X Xue, J M Hung, H Y Kao et al. A 22nm 4Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7 TOPS/W for tiny AI edge devices. 2021 IEEE International Solid-State Circuits Conference, 245(2021).

[33] Q Liu, B Gao, P Yao et al. A fully integrated analog ReRAM based 78.4 TOPS/W compute-in-memory chip with fully parallel MAC computing. 2020 IEEE International Solid-State Circuits Conference, 500(2020).

[34] Y C Chiu, C S Yang, S H Teng et al. A 22nm 4Mb STT-MRAM data-encrypted near-memory computation macro with a 192GB/s read-and-decryption bandwidth and 25.1-55.1 TOPS/W 8b MAC for AI operations. 2022 IEEE International Solid-State Circuits Conference, 178(2022).

[35] W S Khwa, Y C Chiu, C J Jhang et al. A 40-nm, 2M-cell, 8b-precision, hybrid SLC-MLC PCM computing-in-memory macro with 20.5-65.0 TOPS/W for tiny-Al edge devices. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[36] M D Tsai, S Y Yang, C Y Yu et al. A 12nm CMOS RF transceiver supporting 4G/5G UL MIMO. 2020 IEEE International Solid-State Circuits Conference, 176(2020).

[37] J Lee, B Kang, S Joo et al. A low-power and low-cost 14nm FinFET RFIC supporting legacy cellular and 5G FR1. 2021 IEEE International Solid-State Circuits Conference, 90(2021).

[38] B Sung, H G Seok, J Kim et al. A single-path digital-IF receiver supporting inter/intra 5-CA with a single integer LO-PLL in 14nm CMOS FinFET. 2022 IEEE International Solid-State Circuits Conference, 440(2022).

[39] T Sowlati, S Sarkar, B Perumana et al. A 60GHz 144-element phased-array transceiver with 51dBm maximum EIRP and ±60° beam steering for backhaul application. 2018 IEEE International Solid-State Circuits Conference, 66(2018).

[40] A Verma, V Bhagavatula, A Singh et al. A 16-channel, 28/39GHz dual-polarized 5G FR2 phased-array transceiver IC with a quad-stream IF transceiver supporting non-contiguous carrier aggregation up to 1.6GHz BW(2022).

[41] E Naviasky, L Iotti, G LaCaille et al. A 71-to-86 GHz packaged 16-element by 16-beam multi-user beamforming integrated receiver in 28nm CMOS. 2021 IEEE International Solid-State Circuits Conference, 218(2021).

[42] V Giannini, M Goldenberg, A Eshraghi et al. A 192-virtual-receiver 77/79GHz GMSK code-domain MIMO radar system-on-chip. 2019 IEEE International Solid-State Circuits Conference, 164(2019).

[43] Z M Duan, B W Wu, C M Zhu et al. A 76-to-81 GHz 2×8 FMCW MIMO radar transceiver with fast chirp generation and multi-feed antenna-in-package array. 2021 IEEE International Solid-State Circuits Conference, 228(2021).

[44] T K Ma, W Deng, Z P Chen et al. A CMOS 76–81-GHz 2-TX 3-RX FMCW radar transceiver based on mixed-mode PLL chirp generator. IEEE J Solid State Circuits, 55, 233(2020).

[45] H Saeidi, S Venkatesh, X Lu et al. THz prism: One-shot simultaneous multi-node angular localization using spectrum-to-space mapping with 360-to-400 GHz broadband transceiver and dual-port integrated leaky-wave antennas. 2021 IEEE International Solid-State Circuits Conference, 314(2021).

[46] I Abdo, C da Gomez, C Wang et al. A 300GHz-band phased-array transceiver using Bi-directional outphasing and hartley architecture in 65nm CMOS. 2021 IEEE International Solid-State Circuits Conference, 316(2021).

[47] V Mangal, P R Kinget. A 0.42nW 434MHz -79.1dBm wake-up receiver with a time-domain integrator. 2019 IEEE International Solid-State Circuits Conference, 438(2019).

[48] G Lee, S Lee, J H Kim et al. A 1.125Gb/s 28mW 2m-radio-range IR-UWB CMOS transceiver. 2021 IEEE International Solid-State Circuits Conference, 302(2021).

[49] J Im, K Zheng, C H A Chou et al. A 112-Gb/s PAM-4 long-reach wireline transceiver using a 36-way time-interleaved SAR ADC and inverter-based RX analog front-end in 7-nm FinFET. IEEE J Solid State Circuits, 56, 7(2021).

[50] M A Kossel, V Khatri, M Braendli et al. An 8b DAC-based SST TX using metal gate resistors with 1.4pJ/b efficiency at 112Gb/s PAM-4 and 8-tap FFE in 7nm CMOS. 2021 IEEE International Solid-State Circuits Conference, 130(2021).

[51] N Kocaman, U Singh, B Raghavan et al. An 182mW 1-60Gb/s configurable PAM-4/NRZ transceiver for large scale ASIC integration in 7nm FinFET technology. 2022 IEEE International Solid-State Circuits Conference, 120(2022).

[52] Y Seual, A Laufer, A Khairj et al. A 1.41 pJ/b 224Gb/s PAM-4 SerDes receiver with 31dB loss compensation. 2022 IEEE International Solid-State Circuits Conference, 114(2022).

[53] J Kim, S Kundu, A Balankutty et al. A 224Gb/s DAC-based PAM-4 transmitter with 8-tap FFE in 10nm CMOS. 2021 IEEE International Solid-State Circuits Conference, 126(2021).

[54] Z Guo, A Mostafa, A Elshazly et al. A 112.5Gb/s ADC-DSP-based PAM-4 long-reach transceiver with >50dB channel loss in 5nm FinFET(2022).

[55] B Y Ye, K Sheng, W X Gai et al. A 2.29 pJ/b 112Gb/s wireline transceiver with RX 4-tap FFE for medium-reach applications in 28nm CMOS. 2022 IEEE International Solid-State Circuits Conference, 118(2022).

[56] R Yousry, E Chen, Y M Ying et al. A 1.7pJ/b 112Gb/s XSR transceiver for intra-package communication in 7nm FinFET technology. 2021 IEEE International Solid-State Circuits Conference, 180(2021).

[57] H Li, G Balamurugan, M Sakib et al. A 3D-integrated microring-based 112Gb/s PAM-4 silicon-photonic transmitter with integrated nonlinear equalization and thermal control(2020).

[58] E Sentieri, T Copani, A Paganini et al. A 4-channel 200Gb/s PAM-4 BiCMOS transceiver with silicon photonics front-ends for gigabit Ethernet applications. 2020 IEEE International Solid-State Circuits Conference, 210(2020).

[59] H Li, J Sharma, C M Hsu et al. A 100Gb/s-8.3dBm-sensitivity PAM-4 optical receiver with integrated TIA, FFE and direct-feedback DFE in 28nm CMOS. 2021 IEEE International Solid-State Circuits Conference, 190(2021).

[60] T Jyo, M Nagatani, J Ozaki et al. A 48GHz BW 22mW/ch linear driver IC with stacked current-reuse architecture in 65nm CMOS for beyond-400Gb/s coherent optical transmitters. 2020 IEEE International Solid-State Circuits Conference, 212(2020).

[61] D Turker, A Bekele, P Upadhyaya et al. A 7.4-to-14 GHz PLL with 54fsrms jitter in 16nm FinFET for integrated RF-data-converter SoCs. 2018 IEEE Int Solid State Circuits Conference, 378(2018).

[62] F Song, Y Zhao, B Wu et al. A fractional-N synthesizer with 110fsrms jitter and a reference quadrupler for wideband 802.11ax. 2019 IEEE Int Solid State Circuits Conference, 264(2019).

[63] X L Geng, Y B Tian, Y Xiao et al. A 25.8GHz integer-N PLL with time-amplifying phase-frequency detector achieving 60fsrms jitter, -252.8 dB FoMJ, and robust lock acquisition performance. 2022 IEEE International Solid-State Circuits Conference, 65, 388(2022).

[64] J Gong, E Charbon, F Sebastiano et al. A low-jitter and low-spur charge-sampling PLL. IEEE J Solid State Circuits, 57, 492(2022).

[65] Z S Yang, Y Chen, S H Yang et al. A 25.4-to-29.5GHz 10.2mW isolated sub-sampling PLL achieving -252.9dB jitter-power FoM and -63 dBc reference spur. 2019 IEEE International Solid-State Circuits Conference, 270(2019).

[66] Z Zhang, G Zhu, C Patrick Yue. A 0.65-V 12–16-GHz sub-sampling PLL with 56.4-fsrms integrated jitter and –256.4-dB FoM. IEEE J Solid State Circuits, 55, 1665(2020).

[67] D G Lee, P P Mercier. A sub-mW 2.4-GHz active-mixer-adopted sub-sampling PLL achieving an FoM of −256 dB. IEEE J Solid-State Circuits, 55, 1542(2020).

[68] J H Seol, K Choo, D Blaauw et al. Reference oversampling PLL achieving −256-dB FoM and −78-dBc reference spur. IEEE J Solid State Circuits, 56, 2993(2021).

[69] X F Yang, C H Chan, Y Zhu et al. A -246dB jitter-FoM 2.4GHz calibration-free ring-oscillator PLL achieving 9% jitter variation over PVT. 2019 IEEE International Solid-State Circuits Conference, 260(2019).

[70] W H Wu, C W Yao, C K Guo et al. A 14-nm ultra-low jitter fractional-N PLL using a DTC range reduction technique and a reconfigurable dual-core VCO. IEEE J Solid State Circuits, 56, 3756(2021).

[71] M Mercandelli, A Santiccioli, A Parisi et al. A 12.5-GHz fractional-N type-I sampling PLL achieving 58-fs integrated jitter. IEEE J Solid State Circuits, 57, 505(2022).

[72] E Thaller, R Levinger, E Shumaker et al. A K-band 12.1-to-16.6GHz subsampling ADPLL with 47.3fsrms jitter based on a stochastic flash TDC and coupled dual-core DCO in 16nm FinFET CMOS. 2021 IEEE International Solid-State Circuits Conference, 64, 451(2021).

[73] C Hwang, H Park, T Seong et al. A 188fsrms-jitter -243dB-FoMjitter 5.2GHz-ring-DCO-based fractional-N digital PLL with a 1/8 DTC-range-reduction technique using a quadruple-timing-margin phase selector. 2022 IEEE International Solid-State Circuits Conference, 378(2022).

[74] A Santiccioli, M Mercandelli, L Bertulessi et al. A 66-fs-rms jitter 12.8-to-15.2-GHz fractional-N Bang-bang PLL with digital frequency-error recovery for fast locking. IEEE J Solid State Circuits, 55, 3349(2020).

[75] J Kim, Y Jo, Y Lim et al. A 104fsrms-jitter and-61 dBc-fractional spur 15GHz fractional-N subsampling PLL using a voltage-domain quantization-error cancelation technique. 2021 IEEE International Solid-State Circuits Conference, 448(2021).

[76] S M Dartizio, F Buccoleri, F Tesolin et al. A 68.6fsrms-total-integrated-jitter and 1.56μs-locking-time fractional-N Bang-Bang PLL based on type-II gear shifting and adaptive frequency switching. 2022 IEEE International Solid-State Circuits Conference, 65, 1(2022).

[77] Y Z Hu, X Chen, T Siriburanon et al. A charge-sharing locking technique with a general phase noise theory of injection locking. IEEE J Solid State Circuits, 57, 518(2021).

[78] Z Zhang, J C Yang, L Y Liu et al. An 18–23 GHz 57.4-fs RMS jitter −253.5-dB FoM sub-harmonically injection-locked all-digital PLL with single-ended injection technique and ILFD aided adaptive injection timing alignment technique. IEEE Trans Circuits Syst I, 66, 3733(2019).

[79] R J Xu, D W Ye, S R Li et al. A 0.021mm2 65nm CMOS 2.5GHz digital injection-locked clock multiplier with injection pulse shaping achieving −79 dBc reference spur and 0.496 mW/GHz power efficiency. 2022 IEEE International Solid-State Circuits Conference, 214(2022).

[80] Z Zhang. CMOS analog and mixed-signal phase-locked loops: An overview. J Semicond, 41, 111402(2020).

[81] F Wang, T W Li, H Wang. A highly linear super-resolution mixed-signal Doherty power amplifier for high-efficiency mm-wave 5G multi-Gb/s communications. 2019 IEEE International Solid-State Circuits Conference, 88(2019).

[82] Z L Ma, K X Ma, K P Wang et al. A 28GHz compact 3-way transformer-based parallel-series Doherty power amplifier with 20.4%/14.2% PAE at 6-/12-dB power back-off and 25.5dBm PSAT in 55 nm bulk CMOS. 2022 IEEE International Solid-State Circuits Conference, 320(2022).

[83] T Y Huang, N S Mannem, S S Li et al. A 26-to-60 GHz continuous coupler-Doherty linear power amplifier for over-an-octave back-off efficiency enhancement. 2021 IEEE International Solid-State Circuits Conference, 354(2021).

[84] X C Li, W H Chen, S Y Li et al. A 110-to-130GHz SiGe BiCMOS Doherty power amplifier with slotline-based power-combining technique achieving >22dBm saturated output power and >10% power back-off efficiency. 2022 IEEE International Solid-State Circuits Conference, 316(2022).

[85] V Qunaj, P Reynaert. A Doherty-like load-modulated balanced power amplifier achieving 15.5dBm average pout and 20% average PAE at a data rate of 18 Gb/s in 28nm CMOS. 2021 IEEE International Solid-State Circuits Conference, 356(2021).

[86] W Zhu, J W Wang, R T Wang et al. A 1V 32.1dBm 92-to-102GHz power amplifier with a scalable 128-to-1 power combiner achieving 15% peak PAE in a 65nm bulk CMOS process. 2022 IEEE International Solid-State Circuits Conference, 318(2022).

[87] L Xiong, T Li, Y Yin et al. A broadband switched-transformer digital power amplifier for deep back-off efficiency enhancement. 2019 IEEE International Solid-State Circuits Conference, 76(2019).

[88] A Y Zhang, M S W Chen. A watt-level phase-interleaved multi-subharmonic switching digital power amplifier achieving 31.4% average drain efficiency. 2019 IEEE International Solid-State Circuits Conference, 74(2019).

[89] B Yang, H J Qian, X Luo. A Watt-level quadrature switched/floated-capacitor power amplifier with back-off efficiency enhancement in complex domain using reconfigurable self-coupling canceling transformer. 2021 IEEE International Solid-State Circuits Conference, 64, 362(2021).

[90] H Wang, T Huang, N S Mannem et al. Power amplifiers performance survey 2000-present. Available. https://gems.ece.gatech.edu/PA_survey.html

[91] L Iotti, A Mazzanti, F Svelto. Insights into phase-noise scaling in switch-coupled multi-core LC VCOs for E-band adaptive modulation links. IEEE J Solid State Circuits, 52, 1703(2017).

[92] H Guo, Y Chen, P I Mak et al. A 0.08mm2 25.5-to-29.9 GHz multi-resonant-RLCM-tank VCO using a single-turn multi-tap inductor and CM-only capacitors achieving 191.6dBc/Hz FoM and 130kHz 1/f3 PN corner. 2019 IEEE International Solid-State Circuits Conference, 410(2019).

[93] H Guo, Y Chen, P I Mak et al. A 5.0-to-6.36GHz wideband-harmonic-shaping VCO achieving 196.9dBc/Hz peak FoM and 90-to-180kHz 1/f3 PN corner without harmonic tuning. 2021 IEEE International Solid-State Circuits Conference, 294(2021).

[94] Y Y Shu, H J Qian, X Gao et al. A 3.09-to-4.04GHz distributed-boosting and harmonic-impedance-expanding multi-core oscillator with-138.9dBc/Hz at 1MHz offset and 195.1dBc/Hz FoM. 2021 IEEE International Solid-State Circuits Conference, 296(2021).

[95] H K Jia, W Deng, P D Guan et al. A 60GHz 186.5dBc/Hz FoM quad-core fundamental VCO using circular triple-coupled transformer with no mode ambiguity in 65nm CMOS. 2021 IEEE International Solid-State Circuits Conference, 1(2021).

[96] H K Jia, R C Ma, W Deng et al. A 53.6-to-60.2GHz many-core fundamental oscillator with scalable mesh topology achieving −136.0dBc/Hz phase noise at 10MHz offset and 190.3dBc/Hz peak FoM in 65nm CMOS. 2022 IEEE International Solid-State Circuits Conference, 154(2022).

[97] A Franceschin, D Riccardi, A Mazzanti. Series-resonance BiCMOS VCO with phase noise of −138dBc/Hz at 1MHz offset from 10 GHz and −190dBc/Hz FoM. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[98] A Bhat, N Krishnapura. A 25-to-38GHz, 195dB FoMT LC QVCO in 65nm LP CMOS using a 4-port dual-mode resonator for 5G radios. 2019 IEEE International Solid-State Circuits Conference, 412(2019).

[99] Y Y Shu, H J Qian, X Luo. A 18.6-to-40.1GHz 201.7dBc/Hz FoMT multi-core oscillator using E-M mixed-coupling resonance boosting. 2020 IEEE International Solid-State Circuits Conference, 272(2020).

[100] J Gong, B Patra, L Enthoven et al. A 0.049mm2 7.1-to-16.8GHz dual-core triple-mode VCO achieving 200dB FoMA in 22nm FinFET. 2022 IEEE International Solid-State Circuits Conference, 152(2022).

[101] K M Lei, P I Mak, R P Martins. Startup time and energy-reduction techniques for crystal oscillators in the IoT era. IEEE Trans Circuits Syst II, 68, 30(2021).

[102] S Iguchi, H Fuketa, T Sakurai et al. Variation-tolerant quick-start-up CMOS crystal oscillator with chirp injection and negative resistance booster. IEEE J Solid State Circuits, 51, 496(2016).

[103] M Ding, Y H Liu, Y Zhang et al. A 95µW 24MHz digitally controlled crystal oscillator for IoT applications with 36 nJ start-up energy and >13× start-up time reduction using a fully-autonomous dynamically-adjusted load. 2017 IEEE International Solid-State Circuits Conference, 90(2017).

[104] K M Lei, P I Mak, R P Martins. A 0.4V 4.8μW 16MHz CMOS crystal oscillator achieving 74-fold startup-time reduction using momentary detuning. 2017 IEEE International Symposium on Circuits and Systems, 1(2017).

[105] K M Lei, P I Mak, M K Law et al. A regulation-free sub-0.5V 16/24MHz crystal oscillator for energy-harvesting BLE radios with 14.2nJ startup energy and 31.8pW steady-state power. 2018 IEEE International Solid-State Circuits Conference, 52(2018).

[106] M Miyahara, Y Endo, K Okada et al. A 64μs start-up 26/40MHz crystal oscillator with negative resistance boosting technique using reconfigurable multi-stage amplifier. 2018 IEEE Symposium on VLSI Circuits, 115(2018).

[107] K M Lei, P I Mak, M K Law et al. A regulation-free sub-0.5-V 16-/24-MHz crystal oscillator with 14.2-nJ startup energy and 31.8-μW steady-state power. IEEE J Solid State Circuits, 53, 2624(2018).

[108] M Ding, Y H Liu, P Harpe et al. A low-power fast start-up crystal oscillator with an autonomous dynamically adjusted load. IEEE Trans Circuits Syst I, 66, 1382(2019).

[109] O Abdelatty, H Bishop, Y Shi et al. A low power bluetooth low-energy transmitter with a 10.5nJ startup-energy crystal oscillator. ESSCIRC 2019 IEEE 45th Eur Solid State Circuits Conference, 377(2019).

[110] M Scholl, T Saalfeld, C Beyerstedt et al. A 32MHz crystal oscillator with fast start-up using dithered injection and negative resistance boost. 2019 IEEE 45th Eur Solid State Circuits Conference, 49(2019).

[111] X Wang, P Mercier. An 11.1nJ-start-up 16/20MHz crystal oscillator with multi-path feedforward negative resistance boosting and optional dynamic pulse width injection(2020).

[112] D Griffith, J Murdock, P T Røine. A 24MHz crystal oscillator with robust fast start-up using dithered injection. 2016 IEEE International Solid-State Circuits Conference, 104(2016).

[113] H Esmaeelzadeh, S Pamarti. A quick startup technique for high-Q oscillators using precisely timed energy injection. IEEE J Solid State Circuits, 53, 692(2018).

[114] B Verhoef, J Prummel, W Kruiskamp et al. A 32MHz crystal oscillator with fast start-up using synchronized signal injection. 2019 IEEE International Solid-State Circuits Conference, 304(2019).

[115] K M Megawer, N Pal, A Elkholy et al. A 54MHz crystal oscillator with 30 × start-up time reduction using 2-step injection in 65nm CMOS. 2019 IEEE International Solid-State Circuits Conference, 302(2019).

[116] J B Lechevallier, R A R van der Zee, B Nauta. Fast & energy efficient start-up of crystal oscillators by self-timed energy injection. IEEE J Solid State Circuits, 54, 3107(2019).

[117] A Karimi-Bidhendi, P Heydari. A study of multi-phase injection on accelerating crystal oscillator start-up. IEEE Trans Circuits Syst II, 67, 2868(2020).

[118] J B Lechevallier, H S Bindra, R A R van der Zee et al. Energy efficient startup of crystal oscillators using stepwise charging. IEEE J Solid State Circuits, 56, 2427(2021).

[119] J Jung, S Oh, J Kim et al. A single-crystal-oscillator-based clock-management IC with 18× start-up time reduction and 0.68ppm/ºC duty-cycled machine-learning-based RCO calibration. 2022 IEEE International Solid-State Circuits Conference, 58(2022).

[120] H Luo, S Kundu, T Huusari et al. A fast startup crystal oscillator using impedance guided chirp injection in 22nm FinFET CMOS. IEEE J Solid State Circuits, 57, 688(2022).

[121] K M Lei, P I Mak, R P Martins. A 0.35-V 5,200-μm2 2.1-MHz temperature-resilient relaxation oscillator with 667fJ/cycle energy efficiency using an asymmetric swing-boosted RC network and a dual-path comparator. IEEE J Solid State Circuits, 56, 2701(2021).

[122] Y Ji, J W Liao, S Arjmandpour et al. A second-order temperature-compensated on-chip R-RC oscillator achieving 7.93ppm/°C and 3.3pJ/Hz in −40°C to 125°C temperature range. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[123] B Murmann. ADC Performance survey 1997–2021. [Online] Available. http://web.stanford.edu/~murmann/adcsurvey.html

[124] L Jie, X Y Tang, J X Liu et al. An overview of noise-shaping SAR ADC: From fundamentals to the frontier. IEEE Open J Solid State Circuits Soc, 1, 149(2021).

[125] J A Fredenburg, M P Flynn. A 90-MS/s 11-MHz-bandwidth 62-dB SNDR noise-shaping SAR ADC. IEEE J Solid State Circuits, 47, 2898(2012).

[126] S L Li, B Qiao, M Gandara et al. A 13-ENOB second-order noise-shaping SAR ADC realizing optimized NTF zeros using the error-feedback structure. IEEE J Solid State Circuits, 53, 3484(2018).

[127] W J Guo, H Y Zhuang, N Sun. A 13b-ENOB 173dB-FOM 2nd-order NS SAR ADC with passive integrators. 2017 Symposium on VLSI Circuits, C236(2017).

[128] Y Z Lin, C Lin, S C Tsou et al. A 40MHz-BW 320MS/s passive noise-shaping SAR ADC with passive signal-residue summation in 14nm FinFET. 2019 IEEE International Solid-State Circuits Conference, 330(2019).

[129] J X Liu, D Q Li, Y Zhong et al. A 250kHz-BW 93dB-SNDR 4th-order noise-shaping SAR using capacitor stacking and dynamic buffering. 2021 IEEE International Solid-State Circuits Conference, 369(2021).

[130] C C Liu, M C Huang. A 0.46mW 5MHz-BW 79.7dB-SNDR noise-shaping SAR ADC with dynamic-amplifier-based FIR-IIR filter. 2017 IEEE International Solid-State Circuits Conference, 466(2017).

[131] L Jie, B Y Zheng, H W Chen et al. A cascaded noise-shaping SAR architecture for robust order extension. IEEE J Solid State Circuits, 55, 3236(2020).

[132] X Y Tang, X X Yang, W D Zhao et al. A 13.5-ENOB, 107-μW noise-shaping SAR ADC with PVT-robust closed-loop dynamic amplifier. IEEE J Solid State Circuits, 55, 3248(2020).

[133] Y S Shu, L T Kuo, T Y Lo. An oversampling SAR ADC with dac mismatch error shaping achieving 105 dB SFDR and 101 dB SFDR over 1 kHz BW in 55 nm cmos. IEEE J Solid State Circuits, 51, 2928(2016).

[134] S Nan. High-order mismatch-shaping in multibit DACs. IEEE Trans Circuits Syst II, 58, 346(2011).

[135] J X Liu, X Wang, Z J Gao et al. A 40kHz-BW 90dB-SNDR noise-shaping SAR with 4 × passive gain and 2nd-order mismatch error shaping. 2020 IEEE International Solid-State Circuits Conference, 158(2020).

[136] Y T Shen, H Y Li, H M Xin et al. A 103-dB SFDR calibration-free oversampled SAR ADC with mismatch error shaping and pre-comparison techniques. IEEE J Solid State Circuits, 57, 734(2022).

[137] K Lee, J Chae, M Aniya et al. A noise-coupled time-interleaved delta-sigma ADC with 4.2 MHz bandwidth, −98 dB THD, and 79 dB SNDR. IEEE J Solid State Circuits, 43, 2601(2008).

[138] L Jie, B Y Zheng, M P Flynn. A calibration-free time-interleaved fourth-order noise-shaping SAR ADC. IEEE J Solid State Circuits, 54, 3386(2019).

[139] H Y Zhuang, J X Liu, N Sun. A fully-dynamic time-interleaved noise-shaping SAR ADC based on CIFF architecture. 2020 IEEE Custom Integrated Circuits Conference, 1(2020).

[140] C Lin, Y Z Lin, C H Tsai et al. An 80MHz-BW 640MS/s time-interleaved passive noise-shaping SAR ADC in 22nm FDSOI process. 2021 IEEE International Solid-State Circuits Conference, 378(2021).

[141] R Kapusta, H Y Zhu, C Lyden. Sampling circuits that break the kT/C thermal noise limit. IEEE J Solid State Circuits, 49, 1694(2014).

[142] Z L Li, A Dutta, A Mukherjee et al. A SAR ADC with reduced kT/C noise by decoupling noise PSD and BW. 2020 IEEE Symposium on VLSI Circuits, 1(2020).

[143] T H Wang, R W Wu, V Gupta et al. A 13.8-ENOB 0.4pF-CIN 3rd-order noise-shaping SAR in a single-amplifier EF-CIFF structure with fully dynamic hardware-reusing kT/C noise cancelation. 2021 IEEE International Solid-State Circuits Conference, 374(2021).

[144] L Jie, H W Chen, B Y Zheng et al. A 100MHz-BW 68dB-SNDR tuning-free hybrid-loop DSM with an interleaved bandpass noise-shaping SAR quantizer. 2021 IEEE International Solid-State Circuits Conference, 167(2021).

[145] J W Nam, M Hassanpourghadi, A Y Zhang et al. A 12-bit 1.6, 3.2, and 6.4 GS/s 4-b/cycle time-interleaved SAR ADC with dual reference shifting and interpolation. IEEE J Solid State Circuits, 53, 1765(2018).

[146] T Jiang, W Liu, F Y Zhong et al. A single-channel, 1.25-GS/s, 6-bit, 6.08-mW asynchronous successive-approximation ADC with improved feedback delay in 40-nm CMOS. IEEE J Solid State Circuits, 47, 2444(2012).

[147] Y Song, Y Zhu, C H Chan et al. A 77dB SNDR 12.5MHz bandwidth 0–1 MASH ΣΔ ADC based on the pipelined-SAR structure. 2018 IEEE Symposium on VLSI Circuits, 203(2018).

[148] J X Liu, S L Li, W J Guo et al. A 0.029mm2 17-FJ/conv.-step CT ΔΣ ADC with 2nd-order noise-shaping SAR quantizer. 2018 IEEE Symposium on VLSI Circuits, 201(2018).

[149] W Shi, J X Liu, A Mukherjee et al. A 3.7mW 12.5MHz 81dB-SNDR 4th-order CTDSM with single-OTA and 2nd-order NS-SAR. 2021 IEEE International Solid-State Circuits Conference, 170(2021).

[150] P Vogelmann, M Haas, M Ortmanns. A 1.1mW 200kS/s incremental ΔΣ ADC with a DR of 91.5dB using integrator slicing for dynamic power reduction. 2018 IEEE International Solid-State Circuits Conference, 236(2018).

[151] S Mohamad, J Yuan, A Bermak. A 102.2-DB, 181.1-dB FoM extended counting analog-to-digital converter with capacitor scaling. IEEE J Solid State Circuits, 55, 1351(2020).

[152] B Wang, S W Sin, U Seng-Pan et al. A 550-μW 20-kHz BW 100.8-dB SNDR linear- exponential multi-bit incremental sigma-delta ADC with 256 clock cycles in 65-nm CMOS. IEEE J Solid State Circuits, 54, 1161(2019).

[153] Y Zhang, C H Chen, T He et al. A 16 b multi-step incremental analog-to-digital converter with single-opamp multi-slope extended counting. IEEE J Solid State Circuits, 52, 1066(2017).

[154] Y Chae, K Souri, K A A Makinwa. A 6.3µW 20b incremental zoom-ADC with 6ppm INL and 1µV offset. 2013 IEEE International Solid-State Circuits Conference, 276(2013).

[155] Y Y Liu, M L Zhao, Y B Zhao et al. A 4.96μW 15b self-timed dynamic-amplifier-based incremental zoom ADC. 2022 IEEE International Solid-State Circuits Conference, 170(2022).

[156] L Jie, M T Zhan, X Y Tang et al. A 0.014mm2 10kHz-BW zoom-incremental-counting ADC achieving 103dB SNDR and 100dB full-scale CMRR. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[157] M A Mokhtar, P Vogelmann, M Haas et al. A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT incremental delta–sigma modulator with differentially reset FIR feedback. ESSCIRC 2019 - IEEE 45th European Solid State Circuits Conference, 87(2019).

[158] S H Wu, Y S Shu, A Y C Chiou et al. A current-sensing front-end realized by A continuous-time incremental ADC with 12b SAR quantizer and reset-then-open resistive DAC achieving 140dB DR and 8ppm INL at 4kS/s. 2020 IEEE International Solid-State Circuits Conference, 154(2020).

[159] M A Mokhtar, A Abdelaal, M Sporer et al. A 0.9-V calibration-free 97dB-SFDR 2-MS/s continuous time incremental delta-sigma ADC utilizing variable bit width quantizer in 28 nm CMOS. 2021 IEEE Custom Integrated Circuits Conference, 1(2021).

[160] L Qi, A Jain, D Y Jiang et al. A 76.6-dB-SNDR 50-MHz-BW 29.2-mW multi-bit CT sturdy MASH with DAC non-linearity tolerance. IEEE J Solid State Circuits, 55, 344(2020).

[161] P Vogelmann, Y Luo, M A Mokhtar et al. Efficient high-resolution nyquist ADCs. In: Next-Generation ADCs, High-Performance Power Management, and Technology Considerations for Advanced Integrated Circuits. Cham: Springer International Publishing, 41(2019).

[162] J A Severin. High-speed analog-to-digital conversion. Amsterdam: Elsevier(1991).

[163] B Hershberg, D Dermit, B van Liempd et al. A 3.2GS/s 10ENOB 61mW ringamp ADC in 16nm with background monitoring of distortion. 2019 IEEE International Solid-State Circuits Conference, 58(2019).

[164] S Devarajan, L Singer, D Kelly et al. A 12b 10GS/s interleaved pipeline ADC in 28nm CMOS technology. 2017 IEEE International Solid-State Circuits Conference, 288(2017).

[165] A M A Ali, H Dinc, P Bhoraskar et al. A 12b 18GS/s RF sampling ADC with an integrated wideband track-and-hold amplifier and background calibration. 2020 IEEE International Solid-State Circuits Conference, 250(2020).

[166] Z H Zheng, L Wei, J Lagos et al. A single-channel 5.5mW 3.3GS/s 6b fully dynamic pipelined ADC with post-amplification residue generation. 2020 IEEE International Solid-State Circuits Conference, 254(2020).

[167] H Shibata, V Kozlov, Z X Ji et al. A 9GS/s 1GHz-BW oversampled continuous-time pipeline ADC achieving −161 dBFS/Hz NSD. 2017 IEEE International Solid-State Circuits Conference, 278(2017).

[168] H Shibata, G Taylor, B Schell et al. An 800MHz-BW VCO-based continuous-time pipelined ADC with inherent anti-aliasing and on-chip digital reconstruction filter. 2020 IEEE International Solid-State Circuits Conference, 260(2020).

[169] W N Jiang, Y Zhu, M L Zhang et al. A 7.6mW 1GS/s 60dB SNDR single-channel SAR-assisted pipelined ADC with temperature-compensated dynamic gm-R-based amplifier. 2019 IEEE International Solid-State Circuits Conference, 60(2019).

[170] A ElShater, C Y Lee, P K Venkatachala et al. A 10mW 16b 15MS/s two-step SAR ADC with 95dB DR using dual-deadzone ring-amplifier. 2019 IEEE International Solid-State Circuits Conference, 70(2019).

[171] T C Hung, J C Wang, T H Kuo. A calibration-free 71.7dB SNDR 100MS/s 0.7mW weighted-averaging correlated level shifting pipelined SAR ADC with speed-enhancement scheme. 2020 IEEE International Solid-State Circuits Conference, 256(2020).

[172] J C Wang, T H Kuo. A 0.82mW 14b 130MS/S pipelined-SAR ADC with a distributed averaging correlated level shifting (DACLS) ringamp and bypass-window backend. 2022 IEEE International Solid-State Circuits Conference, 162(2022).

[173] X Y Tang, X X Yang, J X Liu et al. A 0.4-to-40 MS/s 75.7 dB-SNDR fully dynamic event-driven pipelined ADC with 3-stage cascoded floating inverter amplifier. 2021 IEEE International Solid-State Circuits Conference, 376(2021).

[174] M L Zhang, C H Chan, Y Zhu et al. A 0.6V 13b 20MS/s two-step TDC-assisted SAR ADC with PVT tracking and speed-enhanced techniques. 2019 IEEE International Solid-State Circuits Conference, 66(2019).

[175] H Y Zhao, F F Dai. A 0.97mW 260MS/s 12b pipelined-SAR ADC with ring-TDC-based fine quantizer for PVT robust automatic cross-domain scale alignment. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[176] Y Song, Y Zhu, C H Chan et al. A 2.56mW 40MHz-bandwidth 75dB-SNDR partial-interleaving SAR-assisted NS pipeline ADC with background inter-stage offset calibration. 2020 IEEE International Solid-State Circuits Conference, 164(2020).

[177] S Baek, I Jang, M Choi et al. A 12b 600MS/s pipelined SAR and 2x-interleaved incremental delta-sigma ADC with source-follower-based residue-transfer scheme in 7nm FinFET. 2021 IEEE International Solid-State Circuits Conference, 172(2021).

[178] H S Zhang, Y Zhu, C H Chan et al. A 25MHz-BW 75dB-SNDR inherent gain error tolerance noise-shaping SAR-assisted pipeline ADC with background offset calibration. 2021 IEEE International Solid-State Circuits Conference, 380(2021).

[179] L X Shen, Y Shen, X Y Tang et al. A 0.01mm2 25µW 2MS/s 74dB-SNDR continuous-time pipelined-SAR ADC with 120fF input capacitor. 2019 IEEE International Solid-State Circuits Conference, 64(2019).

[180] M T Zhan, L Jie, X Y Tang et al. A 0.004mm2 200MS/S pipelined SAR ADC with kT/C noise cancellation and robust ring-amp. 2022 IEEE International Solid-State Circuits Conference, 164(2022).

[181] M L Zhang, Y Zhu, C H Chan et al. A 4× interleaved 10GS/s 8b time-domain ADC with 16 × interpolation-based inter-stage gain achieving >37.5dB SNDR at 18GHz input. 2020 IEEE International Solid-State Circuits Conference, 252(2020).

[182] J Z Liu, M Hassanpourghadi, M S W Chen. A 10GS/s 8b 25fJ/c-s 2850μm2 two-step time-domain ADC using delay-tracking pipelined-SAR TDC with 500fs time step in 14nm CMOS technology. 2022 IEEE International Solid-State Circuits Conference, 160(2022).

[183] C Schaef, S Weng, B Choi et al. A 93.8% peak efficiency, 5V-input, 10A max ILOAD flying capacitor multilevel converter in 22nm CMOS featuring wide output voltage range and flying capacitor precharging. 2019 IEEE International Solid-State Circuits Conference, 146(2019).

[184] S S Amin, P P Mercier. A fully integrated Li-ion-compatible hybrid four-level DC-DC converter in 28-nm FDSOI. IEEE J Solid State Circuits, 54, 720(2019).

[185] A Abdulslam, P P Mercier. A symmetric modified multilevel ladder PMIC for battery-connected applications. IEEE J Solid State Circuits, 55, 767(2020).

[186] Z Y Xia, J Stauth. A two-stage cascaded hybrid switched-capacitor DC-DC converter with 96.9% peak efficiency tolerating 0.6V/μs input slew rate during startup. 2021 IEEE International Solid-State Circuits Conference, 256(2021).

[187] W C Liu, P H Ng, R Pilawa-Podgurski. A three-level boost converter with full-range auto-capacitor-compensation pulse frequency modulation. IEEE J Solid State Circuits, 55, 744(2020).

[188] J Baek, T Nomiyama, S Park et al. A voltage-tolerant three-level buck-boost DC-DC converter with continuous transfer current and flying capacitor soft charger achieving 96.8% power efficiency and 0.87µs/V DVS rate. 2020 IEEE International Solid-State Circuits Conference, 202(2020).

[189] M Choi, D K Jeong. A 92.8%-peak-efficiency 60A 48V-to-1V 3-level half-bridge DC-DC converter with balanced voltage on a flying capacitor. 2020 IEEE International Solid-State Circuits Conference, 296(2020).

[190] P Assem, W C Liu, Y T Lei et al. Hybrid dickson switched-capacitor converter with wide conversion ratio in 65-nm CMOS. IEEE J Solid State Circuits, 55, 2513(2020).

[191] M Ashourloo, V R Namburi, G V Piqué et al. A masterless fault-tolerant hybrid dickson converter with 95.3% peak efficiency 20V-to-60V input and 3.3V output for 48V multi-phase automotive applications. 2021 IEEE International Solid-State Circuits Conference, 258(2021).

[192] Y Yamauchi, T Sai, K Hata et al. 0.55 W, 88%, 78 kHz, 48 V-to-5 V fibonacci hybrid DC–DC converter IC using 66 mm3 of passive components with automatic change of converter topology and duty ratio for cold-crank transient. IEEE Trans Power Electron, 36, 9273(2021).

[193] X Yang, L H Zhao, M L Zhao et al. A 5V input 98.4% peak efficiency reconfigurable capacitive-sigma converter with greater than 90% peak efficiency for the entire 0.4~1.2V output range. 2022 IEEE International Solid-State Circuits Conference, 108(2022).

[194] A Abdulslam, P P Mercier. A continuous-input-current passive-stacked third-order buck converter achieving 0.7W/mm2 power density and 94% peak efficiency. 2019 IEEE International Solid-State Circuits Conference, 148(2019).

[195] A Abdulslam, P P Mercier. A 98.2%-efficiency reciprocal direct charge recycling inductor-first DC-DC converter. 2021 IEEE International Solid-State Circuits Conference, 264(2021).

[196] A Abdulslam, P P Mercier. A battery-connected inductor-first flying capacitor multilevel converter achieving 0.77W/mm2 and 97.1% peak efficiency. 2021 IEEE Custom Integrated Circuits Conference, 1(2021).

[197] C Hardy, H P Le. A 10.9W 93.4%-efficient (27W 97%-efficient) flying-inductor hybrid DC-DC converter suitable for 1-cell (2-cell) battery charging applications. 2019 IEEE International Solid-State Circuits Conference, 150(2019).

[198] N Tang, B Nguyen, Y Y Tang et al. Fully integrated buck converter with 78% efficiency at 365mW output power enabled by switched-inductor capacitor topology and inductor current reduction technique. 2019 IEEE International Solid-State Circuits Conference, 152(2019).

[199] Y Huh, S W Hong, G H Cho. A hybrid structure dual-path step-down converter with 96.2% peak efficiency using 250-mΩ large-DCR inductor. IEEE J Solid State Circuits, 54, 959(2019).

[200] J Y Ko, Y Huh, M W Ko et al. A 4.5V-input 0.3-to-1.7V-output step-down always-dual-path DC-DC converter achieving 91.5%-efficiency with 250mΩ-DCR inductor for low-voltage SoCs. 2021 Symposium on VLSI Circuits, 1(2021).

[201] G G Cai, Y Lu, R Martins. A battery-input sub-1V output 92.9% peak efficiency 0.3A/mm2 current density hybrid SC-parallel-inductor buck converter with reduced inductor current in 65nm CMOS. 2022 IEEE International Solid-State Circuits Conference, 312(2022).

[202] S Zhen, R Yang, D Wu et al. Design of hybrid dual-path DC-DC converter with wide input voltage efficiency improvement. 2021 IEEE International Symposium on Circuits and Systems, 1(2021).

[203] K Hata, Y Yamauchi, T Sai et al. 48V-to-12V dual-path hybrid DC-DC converter. 2020 IEEE Applied Power Electronics Conference and Exposition, 2279(2020).

[204] D Yan, X G Ke, D B Ma. Direct 48-/ 1-V GaN-based DC–DC power converter with double step-down architecture and master–slave AO2T control. IEEE J Solid State Circuits, 55, 988(2020).

[205] K Wei, Y Ramadass, D B Ma. Direct 12 V/24 V-to-1 V tri-state double step-down power converter with online VCF rebalancing and in situ precharge rate regulation. IEEE J Solid State Circuits, 56, 2416(2021).

[206] T X Hu, M Huang, Y Lu et al. A 4A 12-to-1 flying capacitor cross-connected DC-DC converter with inserted D>0.5 control achieving >2× transient inductor current slew rate and 0.73× theoretical minimum output undershoot of DSD. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[207] H X Cao, X Yang, C K Xue et al. A 12-level series-capacitor 48-1 V DC–DC converter with on-chip switch and GaN hybrid power conversion. IEEE J Solid State Circuits, 56, 3628(2021).

[208] L Cheng, K Tang, W H Ki et al. Fast-transient techniques for high-frequency DC–DC converters. J Semicond, 41, 112402(2020).

[209] K Wei, D B Ma. A 10-MHz DAB hysteretic control switching power converter for 5G IoT power delivery. IEEE J Solid State Circuits, 56, 2113(2021).

[210] T H Kuo, Y W Huang, P Y Wang. Background capacitor-current-sensor calibration of DC-DC buck converter with DVS for accurately accelerating load-transient response. 2019 IEEE International Solid-State Circuits Conference, 430(2019).

[211] M Choi, C H Kye, J Oh et al. A synthesizable digital AOT 4-phase buck voltage regulator for digital systems with 0.0054mm2 controller and 80 ns recovery time. 2019 IEEE International Solid-State Circuits Conference, 432(2019).

[212] B Lee, M K Song, A Maity et al. A 25-MHz four-phase SAW hysteretic control DC–DC converter with 1-cycle active phase count. IEEE J Solid State Circuits, 54, 1755(2019).

[213] J H Cho, D K Kim, H H Bae et al. A 1.23W/mm 83.7%-efficiency 400MHz 6-phase fully integrated buck converter in 28nm CMOS with on-chip capacitor dynamic re-allocation for inter-inductor current balancing and fast DVS of 75mV/ns. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[214] C Schaef, T Salus, R Rayess et al. A Imax, fully integrated multi-phase voltage regulator with 91.5% peak efficiency at 1.8 to 1V, operating at 50MHz and featuring a digitally assisted controller with automatic phase shedding and soft switching in 4nm class FinFET CMOS. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[215] J Y Yuan, Z G Liu, F Wu et al. A 12V/24V-to-1V DSD power converter with 56mV droop and 0.9μs 1% settling time for a 3A/20ns load transient. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[216] M Huang, Y Lu, T X Hu et al. A hybrid boost converter with cross-connected flying capacitors. IEEE J Solid State Circuits, 56, 2102(2021).

[217] K Nishijima, K Harada, T Nakano et al. Analysis of double step-down two-phase buck converter for VRM. INTELEC 05 - Twenty-Seventh International Telecommunications Conference, 497(2005).

[218] L Chen, J Sankman, R Mukhopadhyay et al. A 50.7% peak efficiency subharmonic resonant isolated capacitive power transfer system with 62mW output power for low-power industrial sensor interfaces. 2017 IEEE International Solid-State Circuits Conference, 428(2017).

[219] J Tang, L Zhao, C Huang. A 68.3% efficiency reconfigurable 400-/800-mW capacitive isolated DC-DC converter with common-mode transient immunity and fast dynamic response by through-powerlink hysteretic control. IEEE International Solid-State Circuits Conference, 242(2022).

[220] P Lombardo, V Fiore, E Ragonese et al. A fully-integrated half-duplex data/power transfer system with up to 40Mb/s data rate, 23mW output power and on-chip 5kV galvanic isolation. 2016 IEEE International Solid-State Circuits Conference, 300(2016).

[221] E Ragonese, N Spina, A Castorina et al. A fully integrated galvanically isolated DC-DC converter with data communication. IEEE Trans Circuits Syst I, 65, 1432(2018).

[222] V Fiore, E Ragonese, G Palmisano. A fully integrated Watt-level power transfer system with on-chip galvanic isolation in silicon technology. IEEE Trans Power Electron, 32, 1984(2017).

[223] W H Qin, X Yang, S Y Ma et al. An 800mW fully integrated galvanic isolated power transfer system meeting CISPR 22 class-B emission levels with 6dB margin. 2019 IEEE International Solid-State Circuits Conference, 246(2019).

[224] Y Zhuo, S Y Ma, T T Zhao et al. A 52% peak-efficiency >1W isolated power transfer system using fully integrated magnetic-core transformer. 2019 IEEE International Solid-State Circuits Conference, 244(2019).

[225] L S Li, X M Fang, R X Wu. An 11MHz fully integrated 5kV isolated DC-DC converter without cross-isolation-barrier feedback. 2020 IEEE International Solid-State Circuits Conference, 292(2020).

[226] D F Pan, G L Li, F T Miao et al. A 1.25W 46.5%-peak-efficiency transformer-in-package isolated DC-DC converter using glass-based fan-out wafer-level packaging achieving 50mW/mm2 power density. 2021 IEEE International Solid-State Circuits Conference, 468(2021).

[227] D F Pan, G L Li, F T Miao et al. A 1.2W 51%-peak-efficiency isolated DC-DC converter with a cross-coupled shoot-through-free class-D oscillator meeting the CISPR-32 class-B EMI standard. 2022 IEEE International Solid-State Circuits Conference, 240(2022).

[228] Devices Analog. AN-0971. Recommendations for Control of Radiated Emissions with isoPower Devices. Rev. C, Accessed on Jan. 1, 2014. https://www.analog.com/media/en/technical-documentation/application-notes/AN-0971.pdf

[229] C Y Ho, S M Lin, C H Meng et al. An 87.1% efficiency RF-PA envelope-tracking modulator for 80MHz LTE-Advanced transmitter and 31dBm PA output power for HPUE in 0.153μm CMOS. 2018 IEEE International Solid-State Circuits Conference, 432(2018).

[230] J S Paek, D Kim, J S Bang et al. An 88%-efficiency supply modulator achieving 1.08μs/V fast transition and 100MHz envelope-tracking bandwidth for 5G new radio RF power amplifier. 2019 IEEE International Solid-State Circuits Conference, 238(2019).

[231] T Nomiyama, Y Youn, Y Choo et al. A 2TX supply modulator for envelope-tracking power amplifier supporting intra- and inter-band uplink carrier aggregation and power class-2 high-power user equipment. 2018 IEEE International Solid-State Circuits Conference, 434(2018).

[232] P Mahmoudidaryan, D Mandal, B Bakkaloglu et al. Wideband hybrid envelope tracking modulator with hysteretic-controlled three-level switching converter and slew-rate enhanced linear amplifier. IEEE J Solid State Circuits, 54, 3336(2019).

[233] P Mahmoudidaryan, D Mandal, B Bakkaloglu et al. A 91%-efficiency envelope-tracking modulator using hysteresis-controlled three-level switching regulator and slew-rate-enhanced linear amplifier for LTE-80 MHz applications. 2019 IEEE International Solid-State Circuits Conference, 428(2019).

[234] X Liu, H Zhang, P K T Mok et al. A multi-loop-controlled AC-coupling supply modulator with a mode-switching CMOS PA in an EER system with envelope shaping. IEEE J Solid State Circuits, 54, 1553(2019).

[235] X Liu, H Zhang, M Zhao et al. A 2.4V 23.9dBm 35.7%-PAE-32.1dBc-ACLR LTE-20MHz envelope-shaping-and-tracking system with a multiloop-controlled AC-coupling supply modulator and a mode-switching PA. 2017 IEEE International Solid-State Circuits Conference, 38(2017).

[236] J Baek, T Nomiyama, S Park et al. A voltage-tolerant three-level buck-boost DC-DC converter with continuous transfer current and flying capacitor soft charger achieving 96.8% power efficiency and 0.87µs/V DVS rate. 2020 IEEE International Solid-State Circuits Conference, 202(2020).

[237] D Kim, J S Bang, J Baek et al. A hybrid switching supply modulator achieving 130MHz envelope-tracking bandwidth and 10W output power for 2G/3G/LTE/NR RF power amplifiers. 2021 IEEE International Solid-State Circuits Conference, 476(2021).

[238] J S Bang, D Kim, J Lee et al. 2-Tx digital envelope-tracking supply modulator achieving 200MHz channel bandwidth and 93.6% efficiency for 2G/3G/LTE/NR RF power amplifiers. 2022 IEEE International Solid-State Circuits Conference, 1(2022).

[239] P Lichtsteiner, C Posch, T Delbruck. A 128×128 120 dB 15 μs latency asynchronous temporal contrast vision sensor. IEEE J Solid State Circuits, 43, 566(2008).

[240] M H Yang, S C Liu, T Delbruck. A dynamic vision sensor with 1% temporal contrast sensitivity and in-pixel asynchronous delta modulator for event encoding. IEEE J Solid State Circuits, 50, 2149(2015).

[241] B Son, Y Suh, S Kim et al. A 640×480 dynamic vision sensor with a 9µm pixel and 300Meps address-event representation. 2017 IEEE International Solid-State Circuits Conference, 66(2017).

[242] Y Suh, S Choi, M Ito et al. A 1280×960 dynamic vision sensor with a 4.95-μm pixel pitch and motion artifact minimization. 2020 IEEE International Symposium on Circuits and Systems, 1(2020).

[243] T Finateu, A Niwa, D Matolin et al. A 1280×720 back-illuminated stacked temporal contrast event-based vision sensor with 4.86µm pixels, 1.066GEPS readout, programmable event-rate controller and compressive data-formatting pipeline. 2020 IEEE International Solid-State Circuits Conference, 112(2020).

[244] C H Li, L Longinotti, F Corradi et al. A 132 by 104 10μm-Pixel 250μW 1kefps dynamic vision sensor with pixel-parallel noise and spatial redundancy suppression. 2019 Symposium on VLSI Circuits, C216(2019).

[245] M Akrarai, N Margotat, G Sicard et al. A novel event based image sensor with spacial and temporal redundancy suppression. 2020 18th IEEE International New Circuits and Systems Conference, 238(2020).

[246] C Brandli, R Berner, M H Yang et al. A 240 × 180 130 dB 3 µs latency global shutter spatiotemporal vision sensor. IEEE J Solid State Circuits, 49, 2333(2014).

[247] C Posch, D Matolin, R Wohlgenannt. A QVGA 143 dB dynamic range frame-free PWM image sensor with lossless pixel-level video compression and time-domain CDS. IEEE J Solid State Circuits, 46, 259(2011).

[248] S S Chen, M H Guo. Live demonstration: CeleX-V: A 1M pixel multi-mode event-based sensor. 2019 IEEE/CVF Conference on Computer Vision and Pattern Recognition Workshops, 1682(2019).

[249] G Taverni, D Paul Moeys, C H Li et al. Front and back illuminated dynamic and active pixel vision sensors comparison. IEEE Trans Circuits Syst II, 65, 677(2018).

[250] D Park, S W Lee, J Han et al. A 0.8µm smart dual conversion gain pixel for 64 megapixels CMOS image sensor with 12k e- full-well capacitance and low dark noise. 2019 IEEE Int Electron Devices Meet, 16.2.1(2019).

[251] K Miyauchi, K Mori, T Isozaki et al. 4.0µm stacked voltage mode global shutter pixels with a BSI LOFIC and a PDAF capability. 2021 International Image Sensor Workshop, R49(2020).

[252] T Hirata, H Murata, H Matsuda et al. A 1-inch 17Mpixel 1000fps block-controlled coded-exposure back-illuminated stacked CMOS image sensor for computational imaging and adaptive dynamic range control. 2021 IEEE International Solid-State Circuits Conference, 120(2021).

[253] Y Sakano, T Toyoshima, R Nakamura et al. A 132dB single-exposure-dynamic-range CMOS image sensor with high temperature tolerance. 2020 IEEE International Solid-State Circuits Conference, 106(2020).

[254] S Blair, N Cui, M Garcia et al. A 120dB dynamic range logarithmic multispectral imager for near-infrared fluorescence image-guided surgery. 2020 IEEE International Symposium on Circuits and Systems, 1(2020).

[255] T Finateu, A Niwa, D Matolin et al. A 1280 × 720 back-illuminated stacked temporal contrast event-based vision sensor with 4.86µm pixels, 1.066GEPS readout, programmable event-rate controller and compressive data-formatting pipeline. 2020 IEEE International Solid-State Circuits Conference, 112(2020).

[256] A Boukhayma, A Caizzone, C Enz. A CMOS image sensor pixel combining deep sub-electron noise with wide dynamic range. IEEE Electron Device Lett, 41, 880(2020).

[257] M Sato, Y Yorikado, Y Matsumura et al. A 0.50e-rms Noise 1.45µm-pitch CMOS image sensor with reference-shared in-pixel differential amplifier at 8.3Mpixel 35fps. 2020 IEEE International Solid-State Circuits Conference, 108(2020).

[258] S F Yeh, K Y Chou, H Y Tu et al. A 0.66 erms− temporal-readout-noise 3-D-stacked CMOS image sensor with conditional correlated multiple sampling technique. IEEE J Solid State Circuits, 53, 527(2018).

[259] J J Ma, D X Zhang, O Elgendy et al. A photon-counting 4Mpixel stacked BSI quanta image sensor with 0.3e- read noise and 100 dB single-exposure dynamic range. 2021 Symposium on VLSI Circuits, 1(2021).

[260] Y Ota, K Morimoto, T Sasago et al. A 0.37W 143dB-dynamic-range 1Mpixel backside-illuminated charge-focusing SPAD image sensor with pixel-wise exposure control and adaptive clocked recharging. 2022 IEEE International Solid-State Circuits Conference, 65, 94(2022).

[261] P Padmanabhan, C Zhang, M Cazzaniga et al. A 256×128 3D-stacked (45nm) SPAD FLASH LiDAR with 7-level coincidence detection and progressive gating for 100m range and 10klux background light. 2021 IEEE International Solid-State Circuits Conference, 64, 111(2021).

[262] O Kumagai, J Ohmachi, M Matsumura et al. A 189×600 back-illuminated stacked SPAD direct time-of-flight depth sensor for automotive LiDAR systems. 2021 IEEE International Solid-State Circuits Conference, 64, 110(2021).

[263] C Niclass, M Soga, H Matsubara et al. A 100-m range 10-frame/s 340×96-pixel time-of-flight depth sensor in 0.18-μm CMOS. IEEE J Solid State Circuits, 48, 559(2013).

[264] M Perenzoni, D Perenzoni, D Stoppa. A 64×64-pixel digital silicon photomultiplier direct ToF sensor with 100Mphotons/s/pixel background rejection and imaging/altimeter mode with 0.14% precision up to 6km for spacecraft navigation and landing. 2016 IEEE International Solid-State Circuits Conference, 118(2016).

[265] D Kim, S Lee, D Park et al. A dynamic pseudo 4-tap CMOS time-of-flight image sensor with motion artifact suppression and background light cancelling over 120klux. 2020 IEEE International Solid-State Circuits Conference, 100(2020).

[266] M S Keel, D Kim, Y Kim et al. A 1.2-mpixel indirect time-of-flight image sensor with 4-tap 3.5-μm pixels for peak current mitigation and multi-user interference cancellation. IEEE J Solid State Circuits, 56, 3209(2021).

[267] K Yasutomi, T Furuhashi, K Sagawa et al. A 38µm range precision time-of-flight CMOS range line imager with gating driver jitter reduction using charge-injection pseudo photocurrent reference. 2022 IEEE International Solid-State Circuits Conference, 65, 100(2022).

[268] A Payne, A Daniel, A Mehta et al. A 512×424 CMOS 3D Time-of-Flight image sensor with multi-frequency photo-demodulation up to 130MHz and 2GS/s ADC. 2014 IEEE International Solid-State Circuits Conference, 134(2014).

[269] C S Bamji, S Mehta, B Thompson et al. IMpixel 65nm BSI 320MHz demodulated TOF image sensor with 3μm global shutter pixels and analog binning. 2018 IEEE International Solid-State Circuits Conference, 94(2018).

[270] M S Keel, D Kim, Y Kim et al. A 4-tap 3.5μm 1.2Mpixel indirect time-of-flight CMOS image sensor with peak current mitigation and multi-user interference cancellation. 2021 IEEE International Solid-State Circuits Conference, 64, 106(2021).

[271] T Okino, S Yamada, Y Sakata et al. A 1200×9006µm 450fps geiger-mode vertical avalanche photodiodes CMOS image sensor for a 250m time-of-flight ranging system using direct-indirect-mixed frame synthesis with configurable-depth-resolution down to 10cm. 2020 IEEE International Solid-State Circuits Conference, 96(2020).

[272] S Park, B Kim, J Cho et al. An 80×60 flash LiDAR sensor with in-pixel histogramming TDC based on quaternary search and time-gated Δ-intensity phase detection for 45m detectable range and background light cancellation. 2022 IEEE International Solid-State Circuits Conference, 98(2022).

[273] B Kim, S Park, J H Chun et al. A 48×40 13.5mm depth resolution flash LiDAR sensor with in-pixel zoom histogramming time-to-digital converter. 2021 IEEE International Solid-State Circuits Conference, 64, 108(2021).

[274] R K Henderson, N Johnston, S W Hutchings et al. A 256×256 40nm/90nm CMOS 3D-stacked 120dB dynamic-range reconfigurable time-resolved SPAD imager. 2019 IEEE International Solid-State Circuits Conference, 106(2019).

[275] B Park, I Park, C Park et al. A 64 × 64 SPAD-based indirect time-of-flight image sensor with 2-tap analog pulse counters. IEEE J Solid State Circuits, 56, 2956(2021).

[276] M S Keel, Y G Jin, Y Kim et al. A VGA indirect time-of-flight CMOS image sensor with 4-tap 7-μm global-shutter pixel and fixed-pattern phase noise self-compensation. IEEE J Solid State Circuits, 55, 889(2020).

[277] F Arute, K Arya, R Babbush et al. Quantum supremacy using a programmable superconducting processor. Nature, 574, 505(2019).

[278] G A Q A Collaborators, F Arute, K Arya et al. Hartree-Fock on a superconducting qubit quantum computer. Science, 369, 1084(2020).

[279] X Xue, B Patra, J P G van Dijk et al. CMOS-based cryogenic control of silicon quantum circuits. Nature, 593, 205(2021).

[280] P Ball. First 100-QUBIT quantum computer enters crowded race. Nature, 599, 542(2021).

[281] K L Pudenz, T Albash, D A Lidar. Error-corrected quantum annealing with hundreds of qubits. Nat Commun, 5, 3243(2014).

[282] E Charbon, F Sebastiano, M Babaie et al. Cryo-CMOS circuits and systems for scalable quantum computing. 2017 IEEE International Solid-State Circuits Conference, 264(2017).

[283] B Patra, R M Incandela, J P G van Dijk et al. Cryo-CMOS circuits and systems for quantum computing applications. IEEE J Solid State Circuits, 53, 309(2018).

[284] J C Bardin, E Jeffrey, E Lucero et al. A 28nm bulk-CMOS 4-to-8GHz 2mW cryogenic pulse modulator for scalable quantum computing. 2019 IEEE International Solid-State Circuits Conference, 456(2019).

[285] B Patra, J P G van Dijk, S Subramanian et al. A scalable cryo-CMOS 2-to-20 GHz digitally intensive controller for 4×32 frequency multiplexed spin qubits/transmons in 22nm FinFET technology for quantum computers. 2020 IEEE International Solid-State Circuits Conference, 304(2020).

[286] J S Park, S Subramanian, L Lampert et al. A fully integrated cryo-CMOS SoC for qubit control in quantum computers capable of state manipulation, readout and high-speed gate pulsing of spin qubits in Intel 22nm FFL FinFET technology. 2021 IEEE International Solid-State Circuits Conference, 208(2021).

[287] D J Frank, S Chakraborty, K Tien et al. A cryo-CMOS low-power semi-autonomous qubit state controller in 14 nm FinFET technology. 2022 IEEE International Solid-State Circuits Conference, 360(2022).

[288] K Kang, D Minn, S Bae et al. A cryo-CMOS controller IC with fully integrated frequency generators for superconducting qubits. 2022 IEEE International Solid-State Circuits Conference, 362(2022).

[289] B Prabowo, G J Zheng, M Mehrpoo et al. A 6-to-8GHz 0.17mW/qubit cryo-CMOS receiver for multiple spin qubit readout in 40nm CMOS technology. 2021 IEEE International Solid-State Circuits Conference, 212(2021).

[290] A Ruffino, Y T Peng, T Y Yang et al. A fully-integrated 40-nm 5-6.5GHz cryo-CMOS system-on-chip with I/Q receiver and frequency synthesizer for scalable multiplexed readout of quantum dots. 2021 IEEE International Solid-State Circuits Conference, 210(2021).

[291] J Gong, Y Chen, F Sebastiano et al. A 200dB FoM 4-to-5GHz cryogenic oscillator with an automatic common-mode resonance calibration for quantum computing applications. 2020 IEEE International Solid-State Circuits Conference, 308(2020).

[292] Y T Peng, A Ruffino, J Benserhir et al. A cryogenic SiGe BiCMOS hybrid class B/C mode-switching VCO achieving 201dBc/Hz figure-of-merit and 4.2GHz frequency tuning range. 2022 IEEE International Solid-State Circuits Conference, 364(2022).

[293] G Kiene, A Catania, R Overwater et al. A 1GS/s 6-to-8b 0.5mW/qubit cryo-CMOS SAR ADC for quantum computing in 40nm CMOS. 2021 IEEE International Solid-State Circuits Conference, 214(2021).

[294] G Y Qu, H Q Wang, Y M Zhao et al. A 0.28mΩ-sensitivity 105dB-dynamic-range electrochemical impedance spectroscopy soc for electrochemical gas detection. 2018 IEEE International Solid-State Circuits Conference, 286(2018).

[295] S Sonmezoglu, M M Maharbiz. A 4.5mm3 deep-tissue ultrasonic implantable luminescence oxygen sensor. 2020 IEEE International Solid-State Circuits Conference, 454(2020).

[296] A F Yeknami, X Y Wang, S Imani et al. A 0.3V biofuel-cell-powered glucose/lactate biosensing system employing a 180nW 64dB SNR passive δς ADC and a 920MHz wireless transmitter. 2018 IEEE International Solid-State Circuits Conference, 284(2018).

[297] M El Ansary, N Soltani, H Kassiri et al. 50nW 5kHz-BW opamp-less ΔΣ impedance analyzer for brain neurochemistry monitoring. 2018 IEEE International Solid-State Circuits Conference, 288(2018).

[298] J Jang, J Lee, K R Lee et al. 4-camera VGA-resolution capsule endoscope with 80Mb/s body-channel communication transceiver and sub-cm range capsule localization. 2018 IEEE International Solid-State Circuits Conference, 282(2018).

[299] J H Park, J S Y Tan, H Wu et al. 1225-channel localized temperature-regulated neuromorphic retinal-prosthesis SoC with 56.3nW/channel image processor. 2020 IEEE International Solid-State Circuits Conference, 508(2020).

[300] Z H Yu, J C Chen, B W Avants et al. An 8.2mm3 implantable neurostimulator with magnetoelectric power and data transfer. 2020 IEEE International Solid-State Circuits Conference, 510(2020).

[301] S Lee, A J Cortese, P Trexel et al. A 330μm × 90μm opto-electronically integrated wireless system-on-chip for recording of neural activities. 2018 IEEE International Solid-State Circuits Conference, 292(2018).

[302] J W Xu, M Konijnenburg, S Song et al. A 665μW silicon photomultiplier-based NIRS/EEG/EIT monitoring ASIC for wearable functional brain imaging. IEEE Trans Biomed Circuits Syst, 12, 1267(2018).

[303] J M Li, Y L Dong, J H Park et al. Human-body-coupled power-delivery and ambient-energy-harvesting ICs for a full-body-area power sustainability. 2020 IEEE International Solid-State Circuits Conference, 514(2020).

[304] T Tang, L Yan, J H Park et al. EEG dust: A BCC-based wireless concurrent recording/transmitting concentric electrode. 2020 IEEE International Solid-State Circuits Conference, 516(2020).