
- Journal of Semiconductors
- Vol. 43, Issue 7, 071401 (2022)
Abstract
Background
With the emerging applications of artificial intelligence (AI), big data, blockchain, internet-of-things (IoT), autonomous driving, drones/robots, metaverse, etc., and also due to the CoVid-19 pandemic makes people working from home and pushes the companies to setup a blended work model with distributed workforce, the demand for integrated circuits (IC) chips sees an explosive growth in recent two years. Needless to say, a tremendous amount of new circuit design challenges appears along with these new applications. Cutting-edge technologies and circuit innovations are the enablers for satisfying the ever-increasing circuit performance specifications, in terms of data rate, precision, resolution, perception capability, intelligence level, and energy efficiency.
China (the Far-East of the world), as the largest consumer of IC chips in the world, strategically focuses on not only the network infrastructures and the terminal equipment, but also the core hardware component — the chip. Driven by the new waves of technology, both the IC design industry and academia in China are catching up. In particular, it seems that the academia goes a little bit faster, as we can find from the data of the number of published papers on the IEEE International Solid-State Circuits Conference (ISSCC) and the Journal of Solid-State Circuits (JSSC), which are the topmost conference and journal in the field of IC design, respectively. Here in this review paper, we invite the active authors from China to provide their humble opinions on the recent trending IC design directions in 2022.
The following contents are categorized into six sections. Section 2 on machine learning and AI chips introduces AI chips for domain-specific applications, and emerging compute-in-memory circuits. Section 3 on communications IC discusses wireless/wireline transceivers, power amplifiers (PAs), clock generators and frequency synthesizers. Section 4 on analog-to-digital (ADC) data converters covers recent promising hybrid ADC architectures, and high-resolution ADCs. Section 5 on integrated power converters focuses on the topology and controller design of switched-inductor-capacitor hybrid power converters, isolated power, and the supply modulator for PA in 5G communication. Section 6 on CMOS imagers and range sensors talks about event-based and high dynamic range image sensors, as well as the time-of-flight (ToF) range sensors. Last but not least, Section 7 on emerging directions leads us to the cryogenic CMOS for qubit and biomedical frontiers. Finally, we draw conclusions in Section 8.
Machine learning and artificial intelligence chips
When people nowadays are working towards to metaverse or the “Matrix”, the first trending direction has to be AI chips. Besides the conventional general AI computer systems, custom processors are becoming more ubiquitous in the machine learning space, motivating the chip design for domain-specific applications, which include voice, image, and some other emerging directions. Meanwhile, computing-in-memory chips, at both the macro-level and system-level, have become an important technical approach for energy-efficient or high-performance AI chips.
AI chips for domain-specific applications
Custom processors are becoming more ubiquitous in the machine learning (ML) space, motivating the chip design for domain-specific applications (DSA). Through the methodology of hardware-software co-optimization, the DSA chips can bring a great leap of performance for target applications. Reviewing the ISSCC publications in recent three years, AI chips for DSA have drawn extensive attention for various applications, including voice, image, and some other emerging directions.
AI chips for voice applications
For voice applications, keyword spotting (KWS) and automatic speech recognition (ASR) can be widely applied to various wearable or mobile devices. For such battery-powered applications, ultra-low power is a strong requirement for voice processing chips. Typically, a KWS or ASR system is composed by the feature extractor and the AI signal processing, and recent works aims at optimizing the power of such two modules in circuit and system level.
Shan[
Although the chip in Ref. [
Different from KWS that only needs to implement small-vocabulary tasks (1–2 words), ASR has to deal with large-vocabular tasks of more than 105 words. As a result, models with bidirectional recurrent neural network (RNN) and attention mechanism are necessary for improving the ASR accuracy. To accelerating ASR, Tambe[
To further reduce the power for IoT platforms, the technology of voice activity detection (VAD) that can gain attention on events-of-interest and is becoming an interesting topic. In such system, the always-on acoustic wakeup detector dominates the overall power consumption since the remainder of the VAD system is power-gated during sleeping time. As a result, an ultra-low-power and wide bandwidth feature extractor with wakeup detection is more important for VAD. Although achieves μW-level power, traditional analog-domain feature extraction-based VADs often adopt a simple decision tree or a fixed neural network for detection, and can only be applied to limited acoustic event targets. In ISSCC’19, Cho[
To realize real-time wakeup decision, Chen[
AI chips for image or video processing
For image or video processing, people paid more attentions to improve the energy and frame efficiency for executing the AI models, with the co-optimization technology of algorithm and architecture, low-bit model quantization and sparse model acceleration.
Lu[
Im[
Compared with image data, video has one more dimension of time and provides more design space in algorithm and hardware. Since adjacent frames share similar information, efficiently leverage video temporal correlations to minimize the computing costs for video model is worth exploring. In ISSCC’20, Yuan[
For emerging AI models, transformers have achieved great success in multiple AI fields, from natural language processing (NLP) to computer vision. Compared with CNN models, transformer calls for larger memory storage and different data reusing mechanism. To develop specific architecture for transformer accelerating, two relative chips are presented in ISSCC’22. Wang[
Also in this year, Tu[
The DSA chips mentioned above mainly follow the road of algorithm-architecture co-optimization. Aiming at one specific applications, they analyze the demand and develop the high-efficiency analog or digital circuits. Inspired by 2.5D/3D stacked integrating technologies for high bandwidth memory fabrication, the road of monolithic 3D and hybrid bonding techniques are also explored for DSA chips. Eki[
Niu[
Based on the reviews above, we can see that significant progresses have been made in machine learning processor design for specific application acceleration.
IEDM, 2019,
| IISW, 2020,
| ISCAS, 2020,
| ISSCC, 2020,
| EDL, 2020,
| JSSC, 2018,
| VLSI, 2021,
| |
---|---|---|---|---|---|---|---|
Sensor type | Multi-gain response | Multi-gain response | Non-linear response | Non-linear response | Low-noise | Low-noise | QIS |
Process | N/A | 45 nm CIS/
| 350 nm CIS | 90 nm CIS/
| 180 nm CIS | 45 nm CIS/
| 45 nm CIS/
|
Pixel array | 64 M | 0.8 M | 0.07 M | 9.2 M | 0.02 M | 8.3 M | 4 M |
Pixel pitch (μm) | N/A | 4 | 15 | 4.86 | NA | 1.1 | 2.2 |
FWC (e-) | 1.2 × 104 | 1.3 × 105 | N/A | N/A | 6.5 × 103 | N/A | 3 × 104 |
Noise (e-) | 1.2 | 4 | N/A | N/A | 0.32 | 0.66 | 0.27 |
DR (dB) | 80 | 90 | 124 | >124 dB | 84.8 | N/A | 100 |
Table 0. Performance summary of the state-of-the-art HDR sensors.
Computing-in-memory chips
Computing-in-Memory (CIM) chips have become an important technical approach for energy-efficient or high-performance AI chips. The recent CIM chips mainly focus on two design levels: the macro-level and system-level CIM chips.
Macro-level CIM chips
The macro-level CIM chips aim at higher energy efficiency, higher density, better accuracy and higher performance. The current-based, charge-based, all-digital, and time-based CIM macro structures have been proposed. The key design concerns include low-power ADC, high-density CIM cell structure, high accuracy, more functionality, etc.
ADC design is critical for an energy-efficient CIM chip as it occupies the majority of the power consumption. Based on the algorithm analysis, the multiply-accumulate (MAC) values of the ADC input concentrate on low values. Therefore, one reference voltage can be adopted for pre-classification, which reduces the ADC sensing bit of low MAC values[
Storage density and computation density are also key features for the CIM macro. For higher computation density, several storage cells are grouped together to share the same local-computing-cell for CIM operation[
Accuracy is an important concern for CIM macro design. For better accuracy, the output ratio, which is the ratio of the real output resolution and the ideal output resolution, is a key parameter for current/charge-based CIM structures[
More functionality is also explored on the CIM macro structures. Several works have explored configurable activation/weight bit-precision, among which the 2’s/non-2’s complementary ADC is designed to support signed/unsigned MAC operations[
IEDM, 2019,
| IISW, 2020,
| ISCAS, 2020,
| ISSCC, 2020,
| EDL, 2020,
| JSSC, 2018,
| VLSI, 2021,
| |
---|---|---|---|---|---|---|---|
Sensor type | Multi-gain response | Multi-gain response | Non-linear response | Non-linear response | Low-noise | Low-noise | QIS |
Process | N/A | 45 nm CIS/
| 350 nm CIS | 90 nm CIS/
| 180 nm CIS | 45 nm CIS/
| 45 nm CIS/
|
Pixel array | 64 M | 0.8 M | 0.07 M | 9.2 M | 0.02 M | 8.3 M | 4 M |
Pixel pitch (μm) | N/A | 4 | 15 | 4.86 | NA | 1.1 | 2.2 |
FWC (e-) | 1.2 × 104 | 1.3 × 105 | N/A | N/A | 6.5 × 103 | N/A | 3 × 104 |
Noise (e-) | 1.2 | 4 | N/A | N/A | 0.32 | 0.66 | 0.27 |
DR (dB) | 80 | 90 | 124 | >124 dB | 84.8 | N/A | 100 |
Table 0. Performance summary of the state-of-the-art HDR sensors.
System-level CIM chips
On the other hand, the system-level CIM chips present more sophisticated CIM architecture with more flexible operator support.
Inter/intra-macro data reuse and channel/kernel-order weight mapping strategies are explored on the CIM architectures for better resource utilization[
Algorithm-hardware co-design method is utilized for higher energy efficiency. For example, the block-wise weight sparsity and dynamic activation sparsity is proposed to apply sparsity techniques on the regular CIM structure[
To support high-precision training application, a reconfigurable unified floating point or integer (FP/INT) CIM processor is proposed[
Various devices based CIM chips
SRAM is one of the most popular devices for CIM chip design, while other devices for CIM are also explored, including conventional storage devices such as DRAM or embedded DRAM (eDRAM), and the emerging non-volatile memory (NVM) devices such as resistive RAM (RRAM), spin-transfer torque magneto-resistive RAM (STT-MRAM), phase-change memory (PCM), etc.
DRAM/eDRAM device is adopted for CIM for its high storage density. Xie[
A three-transistor, one-capacitor (3T1C) dynamic analog RAM (DARAM) structure is proposed[
RRAM is another well-explored device with macro-level and system-level chip verification. From 2020 to 2022, the foremost storage capacity of RRAM-based CIM macro increases from 2, 4, to 8 Mbit[
Spin-transfer torque magneto-resistive RAM (STT-MRAM)[
Figure 1.(Color online) Comparison of the state-of-the-art CIM macros (scaled to 4-bit input, 4-bit weight), with (a) energy efficiency and area efficiency, and (b) performance and storage capacity.
In summary, the CIM chip has become an emerging technology route for more energy-efficient computing and high-performance AI applications, which shows competitive or higher energy efficiency compared with the digital NN processor. The macro/system-level CIM chip keeps moving towards better macro metrics (power, area, performance, accuracy, functionality) and sophisticated CIM architecture with more operator support. CIM on various devices and specific applications is also a promising direction.
Communication ICs
Telecommunication industry has been growing explosively over the past few decades. Communication ICs, ranging from block-level circuits to system-level transceivers, have attracted intensive attention from both academia and industry. This section covers the latest research trends of communication ICs during the past few years, which includes the following sub-topics: 1) wireless transceivers, 2) wireline and optical communication circuits, 3) phase-locked loops, 4) critical building blocks including power amplifiers, voltage-controlled oscillators, and crystal oscillators.
Wireless transceiver ICs
Wireless transceivers are central components of wireless systems. For mobile communication applications, the continuous demand for faster wireless data in the context of mobile battery limitations drives the development of high-throughput and energy-efficient wireless transceivers in more carrier aggregation and wider bandwidth per path, as shown in
Figure 2.(Color online) Trends of the number of CA from downlink path and maximum BW per path for recent cellular SoC implementations.
5G radio technology promises tens of Gb/s data-rates with a 10× reduction of latency. This will enable applications in enhanced mobile broadband, massive internet of things and mission-critical services. In Ref. [
Millimeter-wave (mm-wave) wireless communication and radar transceiver systems are the key drivers for cutting-edge integrated circuits design advancement. Mm-wave antenna arrays allow fine beam steering with large radiated power and compact size. Scalability of large-scale arrays to hundreds of elements is necessary to extend the range of mm-wave for 5G and the next-generation radio systems. In Ref. [
Advances in the ultra-low-power radio continue the drive towards power-efficiency and high sensitivity wireless nodes. In Ref. [
Wireline and optical communication circuits
With the development of cloud services and mobile computing, the datacenter drives an ever-growing demand for the high-speed and low power interconnects. In the past three years, the wireline I/Os have witnessed a doubled per-channel data-rate, scaling from 112 to 224 Gb/s. The four-level pulse amplitude modulation (PAM-4) has been employed as an enabling technique. To keep the power consumption acceptable, some of the most advanced processes have been utilized, scaling from 7-nm to 5-nm FinFET technology. A universal figure-of-merit factor, pico-Joule-per-bit (pJ/bit), has been widely adopted to evaluate the power efficiency. The trends of wireline communication circuits is briefly summarized in
Figure 3.(Color online) Trends of wireline communication circuits: power efficiency and data rate.
Categorized by the communication distance, wireline transceivers employ different wiring channels (copper or fiber) and circuity topologies. In the past three years, the long-reach (LR) and extra short reach (XSR) serializer/deserializer (SerDes), as well as the co-packaged optics (CPO) have attracted the most research attentions worldwide.
LR and XSR SerDes
The LR Serdes attempts to overcome up to 40-dB channel loss and beyond 112 Gb/s channel speed. State-of-the-art LR receivers have largely converged on an architecture based on time-interleaved SAR ADCs (RX) and multi-bit equalizer embedded DACs (TX). There are two fundamental design challenges need to be addressed in the SerDes transceivers. Firstly, the data path analog bandwidth keeps increasing, while maintaining about 1-Vpp output swing and sufficient linearity for the PAM-4 signaling. Inverter-based analog front-end circuits are widely adopted to accommodate the advanced CMOS technology[
High-performance XSR SerDes with both high area efficiency (mm2/lane) and energy efficiency (pJ/b) are driven by the interconnects in datacenter, XPU and AI applications. It enables chiplets, multi-die integration for low cost, high yield, and high throughput. The XSR SerDes employs simplified TX DAC and RX DSP functions to save power and area. In Ref. [
Optical links and silicon photonics
The datacenter switch throughput has been growing from 12.8 to 25.6 Tb/s. To support inter- and intra-rack interconnects, the optical links are expected to achieve longer reach (<500 m) at higher data rate (>400 Gb/s). Silicon photonics (Si-Ph) solutions are of particular interest to achieve high-density integrated 100+ Gb/s/λ optical transceivers, which would be deployed in the CPO modules[
In conclusion, after three years of continuous research, the 112 Gb/s/lane wireline circuits have become mature. To save power and further double the speed, more advanced 5-nm CMOS process starts to be adopted as a mainstream technology, enabling the exploring for 224 Gb/s/channel. The full link (TX+RX) power efficiency of 112G LR SerDes has reached 2.2 pJ/bit, while the 224G is still beyond 3 pJ/bit. Optical links would be utilized to replace the copper-wire for meter-scale connectivity and beyond. By co-packaging electronics and silicon photonics, chip-scale high-BW and high-density throughput would be feasible in the future.
Low-jitter PLL
Phase-locked loops (PLL) are widely used in modern ultra-high speed wireless/wireline communication circuits and systems, such as 5G transceivers, over-100-Gbps SerDes transceivers, and high sampling rate analog-to-digital converters (ADCs).
Figure 4.(Color online) The jitter variance versus power of the recently published PLLs from ISSCC/JSSC.
Among the PLLs shown in
The CPPLL, which adopts a phase/frequency detector (PFD) with unlimited phase and frequency detection range, is simple and robust[
Figure 5.Simplified PLL linear phase noise model with its noise transfer function of the PD.
As discussed before, it is significant to increase the PD gain so as to suppress the in-band phase noise to achieve low-jitter with low power consumption. The SSPLLs[
Digital PLL is getting more popular due to its scalability in advanced CMOS technology and the design portability between technologies. TDC-based PLL[
To relax the power consumption issue, the D-SSPLL/D-SPLLs[
Besides the PLLs introduced above, the ILCM is also a low-cost solution to achieve low-jitter performance by simply injecting a clean pulse to the oscillator to simultaneously suppress the in-band and output phase noise of the PLL[
As discussed above, the SSPLL/SPLL (including analog and digital architectures) and the ILPLL/ILCM, achieve better performance than the CPPLLs in terms of jitter and FoMjitter. However, actually, the CPPLL is still the most widely used architecture in the industry. The main reason is that the unlimited locking range makes the CPPLL robust to maintain its locking state over any disturbance[
In summary, both analog and digital sampling/sub-sampling PLLs are popular for low-jitter low-power PLL design, because the analog SSPLL/SPLL achieves the best FoMjitter of –259.2 dB and lowest integrated jitter of sub-50 fs, and also dominate the state-of-the-art PLL performance; the digital sampling/sub-sampling PLLs can effectively reduce the performance gap between analog and digital PLLs with the advantage of smaller area. In addition, the development of spur reduction technique makes the ILPLL or ILCM become attractive as a low-cost low-jitter clock generation solution; and the continuous research on the fast relock technique is improving the robustness of the SSPLL/SPLL and ILPLL/ILCM.
Critical building blocks in communication system
In this subsection, we are going to discuss some commonly used critical building blocks in communication systems, including power amplifiers, voltage-controlled oscillators, and crystal oscillators.
Power amplifiers
Power amplifiers (PAs) are still one of the most important building blocks in wireless transceivers since it dominates the power consumption of transmitters. Therefore, PA is currently a very active research area. Various PAs spanning from RF bands to terahertz bands towards higher efficiency, higher output power, more compact chip area, and so on are published in recent year’s ISSCC and JSSC, including millimeter-wave (mm-wave) CMOS PAs with Watts-level output power, both digital and analog PAs with back-off efficiency enhancement, large-scale power-combining CMOS PA, wideband PAs, and mm-wave PA in GaN HEMT process and in CMOS FinFET process.
Figure 6.(Color online) The state-of-the-art PA peak PAE and Psat performance in different processes[
For mm-wave linear PAs, the Doherty architecture, been invented in 1936 and hot for several decades, is still the most popular technique to improve the back-off efficiency nowadays. Various Doherty PA implementations on silicon have been demonstrated[
For digital PAs, the switched-capacitor PA (SCPA) has been the dominated architecture due to its easy implementation, well matching, and flexibility. Recent researches about the SCPA focus on the back-off efficiency enhancement method such as Doherty power-combining, subharmonic switching, and floated-capacitor techniques. Transformer-based power-combining networks introduces Doherty-like operation into SCPAs[
Voltage-controlled oscillators
The emerging 5G communication sets a stringent requirement for the phase noise of the local oscillator (LO). As calculated in Ref. [
Figure 7.(Color online) The state-of-the-art oscillator FoM and FoMT at 1MHz offset versus frequency.
Harmonic tuning techniques such as class-F, tail filtering, and implicit common-mode resonance have already been proven to be efficient in phase noise improvement, which has been further exploited in recent years[
It is well known that an N core oscillator can improve the phase noise by 10log(N) times. In Ref. [
This year, the series resonance VCO presented in Ref. [
Besides low-phase noise, very wide FTR VCOs are also attractive to support the widely distributed frequency bands allocated for 5G communication. Usually one octave FTR is considered sufficient since all lower frequencies can be generated by cascaded frequency dividers, whose design cost is low. The most straightforward way to improve the FTR of an LC oscillator is to scale up the size of the switched-capacitor arrays to improve the max-to-min capacitance ratio. However, this solution faces the fundamental trade-off between the on-resistance and off-capacitance of the transistor switches, which translates to the trade-off between the max-to-min capacitance ratio and the tank Q and the trade-off between the FTR and phase noise. On the other hand, the mode-switching technique[
The mode-switching technique has been proven to be successful in wide FTR VCOs. However, two major design challenges remain. The first is to further reduce the parasitic capacitance introduced by the mode-switching technique, such as the coupling capacitors in Ref. [
Crystal oscillators for IoT devices
Lowering the startup time (ts) and energy (Es) of the crystal oscillator (XO) for the IoT devices has been an emerging and popular trend in recent years[
In this regard, there is a thrust to radically improve the ts and Es of the XO, as shown in
Figure 8.(Color online) The trends of (a) startup time and (b) startup energy of the MHz-range fast startup XO.
Instead of waiting for the crystal to accumulate its amplitude, the quintessence of energy injection technique is to pour energy into the crystal by exciting it with an auxiliary signal[
Stimulated by the expansion of the ultra-low-power IoT market, we expect that the research on the fast startup technique for the XO will continue to be active in 2022 and beyond. Even though the ts of the fast startup XOs implemented recently are close to the theoretical minimum, for instance, a mere 17% of the Es is delivered to the core of the crystal[
Data converters
There have been significant advances in the design of data converters over the past decade. This review article covers three major directions as demonstrated in latest ISSCC works. The first one is a novel hybrid architecture called noise-shaping successive approximation register (SAR) ADCs. The second is high-resolution incremental ADC. Last but not least, state-of-the-art pipelined ADC developments will also be reviewed.
Noise-shaping SAR ADCs
The noise-shaping SAR (NS-SAR) is a promising hybrid architecture emerged in past few years. NS-SAR is a hybridization of the SAR and the delta-sigma (DS) architectures, and it benefits from the both side: it is low-power and area-efficient like SAR, and provides high SNR as DS ADCs. NS-SAR is also easy to down-scale and good for advanced CMOS processes.
Figure 9.(Color online) Comparison between NS-SAR and conventional architectures.
Figure 10.(Color online) Schreier figure-of-merit (FoMs) and bandwidth (BW) of NS-SAR over years.
Figure 11.(Color online) (a) The basic framework of NS-SAR, and (b) its signal model.
However, in NS-SAR, EN1, ED and ES are not suppressed, and EN2 is only suppressed by the EF loop. Since HEF is on the numerator of the NTF, a simple FIR HEF can implement the zeros in NTF, making EF-NS-SAR simple in implementation. HCIFF is on the denominator of the NTF and it needs high gain integrators to suppress EQ. However, EF-NS-SAR is more sensitive to filter-gain because HEF should be close to 1 in the signal band. CIFF-NS-SAR is more tolerant to variation as long as HCIFF is large enough.
Despite the advantages over DS ADC, NS-SAR also has various challenges, which are the main focus of current research. The main challenges in NS-SAR architecture are in four aspects: loop filter, DAC mismatch, bandwidth limitations, and kT/C noise.
Loop filter
The loop filter is the most critical analog block in NS-SAR, and it dominates the SNR and power efficiency. For efficiency and scaling purpose, the loop filter in NS-SAR is usually opamp-free and uses simpler alternative schemes. Many recent NS-SAR designs adopt passive switched-capacitor loop filters as they are simple, linear, PVT robust, efficient, and scaling-friendly. But passive filter is not able to provide sufficient loop gain, and thus additional active gain is usually necessary for high performance noise-shaping, including: 1) Opamp is used in some early NS-SARs[
Another popular scheme is using optimized active amplifiers, such as dynamic gm-C amplifiers[
DAC mismatch
DAC mismatch causes significant accuracy degradation in NS-SAR and it cannot be suppressed by noise shaping. A direct scheme of reducing the DAC mismatch is enlarging the DAC. But it is too costly and is rarely practical. Another popular method is digital calibration, either in foreground or background. However, foreground calibration takes extra testing cost and cannot deal with real-time variations; background calibration can track variations in real-time, but it is much more complicated and converges slower.
Mismatch-shaping (MS) is another solution to DAC mismatch for oversampled ADCs such as NS-SAR. It does not rely on the prior knowledge or measurement of the mismatch. There are two popular MS schemes: dynamic element matching (DEM) and mismatch error shaping (MES)[
DEM is based on an element selection logic (ESL) that activates the DAC elements in a certain pattern, such that the mismatch error is irrelevant to the DAC code and suppressed in-band. Data weighted averaging (DWA) is one of the most popular ESL that 1st-order shapes the mismatch error, and some advanced ESL techniques[
In contrast, MES captures the mismatch error in the analog domain and feeds it back for noise-shaping. Specifically, we can preset the CDAC's least significant bits (LSBs) before sampling, such that the mismatch error from the previous conversion is captured and subtracted in the current conversion, and the preset LSBs are then subtracted from the current digital output. Compared to DEM, MES is relatively simple and works for binary DAC. The main drawback of MES is that the presetting of the CDAC also feeds back the previous input signal, which occupies a part of the input range. This issue can be mitigated by using larger bits of MSB[
Bandwidth limitation
Due to oversampling and the multi-cycle SAR conversion, NS-SAR trends to be limited in bandwidth. Time-interleaving (TI) is a common solution to increase the sampling rate, but TI is not compatible with noise-shaping ADC because of the memory effect in them. Some early examples of interleaved noise-shaping ADC[
TI-NS-SARs can be implemented in EF form[
kT/C noise
Another challenge in NS-SAR is the input sampling. Since the kT/C noise is not shaped, a large CDAC is necessary in high-resolution ADCs, which brings a large burden on the input driver. Oversampling reduces kT/C noise by the OSR, thus the sampling capacitor can be OSR-times smaller. But as the sampling frequency increased, the input driver has to charge the capacitor faster and is not fully relaxed.
There are two techniques to reduce the kT/C noise[
NS-SAR directions
There still remain many interests in NS-SAR research regarding the following topics: 1) Higher speed, 2) higher resolution, 3) reference buffer, and 4) further hybridization.
1) The highest reported NS-SAR BW is only 80 MHz (with interleaving)[
2) For higher resolution, few published NS-SARs can achieve >100 dB SNDR so far, but many applications, such as audio and sensing, requires dynamic range over 120 dB. Advanced mismatch-shaping or low-cost background calibration is the key to this goal.
3) Most NS-SAR design relies on massive reference decoupling capacitors and rarely discuss practical reference generation. It remains chances to co-design a reference buffer optimized for NS-SAR, which might be beneficial as NS-SAR emphasizes an accurate residue at the end of conversion, and has a higher tolerance to the reference error during conversion.
4) NS-SAR can be further hybridized with other architectures. NS-pipeline-SAR[
High resolution incremental ADCs
In recent research developments of high-resolution data converters, the incremental converter (IADC) is one of the excellent candidates to achieve high resolution with the trade-off of reduced bandwidth. Also, different from its delta–sigma counterparts, the IADC incorporates a reset operation in its analog integrators and digital decimators. It exhibits a Nyquist ADC property in terms of out-of-band noise processing, allows multiplexing, and leads to a simple decimation filter and thus significantly reducing the latency in digital post-processing. The recent development trend of IADCs will be qualitatively discussed below.
Slicing or reconfigurable IADCs
In the delta-sigma modulators or IADCs, the first integrators occupied the most power consumption because of the thermal noise considerations. The later stages’ performance were benefited from the gain of the first stage, and their capacitors can be selected with a small size. As a result, reconfigurations of the loop filters are proposed in works[
Figure 12.(Color online) Block diagram of DT-Slicing IADC in Ref. [
Exponential IADCs
The resolution of traditional incremental ADCs can be improved by cascading the integrators with increasing orders, resulting in a faster accumulation. The modulator accumulates from linearly to bi-quadratically with increasing oversampling ratio (OSR) from 1st- to 4th-order IADCs. Straightforwardly, one can build an exponential growth of accumulation (instead of order-based accumulation), which is the fastest way by nature. However, the exponential accumulation dramatically reduced the required OSR by emphasizing the strong accumulation weights at the beginning of the accumulation cycles, causing penalties in the thermal noise and mismatch averaging efforts in DWA. As a result, the fast exponential accumulation simultaneously served as the pros and cons for such architecture at the same time. The noise and mismatch averaging penalty factors range from 1 to 2.3 from 1st- to 4th-order IADCs, and for the exponential accumulation, the effort of oversampling is completely killed[
Indeed, for high-resolution IADCs, there are two kinds of fundamental noises required to be suppressed during the conversion: the smaller thermal noise and the larger quantization noise. The oversampling ratio can only reduce the thermal noise (given a fixed capacitance), while a faster accumulation growth can suppress the quantization noise. As illustrated in
Figure 13.(Color online) Block diagram of DT Linear-Exponential IADC in Ref. [
Hybrid IADCs
High-order incremental ADCs provide faster accumulation but induce thermal noise penalty. On the other hand, hybrid architectures are developed to overcome the long conversion time of low-order (≤2) IADCs. The basic concept of the hybrid IADC is to digitalize the residue of the coarse ADC further to reduce the final quantization noise in the output of the ADC. The residue estimation will combine with the decimated output bit-stream in the digital domain, canceling the quantization error. In a work[
Zoom IADCs[
Figure 14.(Color online) Block diagram of DT-Zoom IADC in Ref. [
Continuous-time IADCs
Continuous-time (CT) IADCs have attracted attention for circuit implementation for their simple driving circuitry and low power consumption. Thanks to the resistive input impedance, the front-end preceding driver does not need to drive the switched-capacitor load. Moreover, the integrators in CT consume lower power than the discrete-time (DT) counterpart.
Its resetting operation is one of the largest differences between the CT IADC and the CT delta-sigma ADC (CTDSM). This results in reduced anti-aliasing performance and the re-settling of the FIR DACs. In CTDSM, since the converter is free-running, the loop filter can be designed and considered as an IIR filter, setting up a satisfactory anti-aliasing rejection. If the FIR DACs are used, the free-running operation of the DAC in CTDSM will perform well in steady-state also. While for the cases of CT-IADCs, the resetting operation causes two issues: 1) the integrator memory is reset, which effectively translate the loop filter as an FIR filter, degrading its anti-aliasing performance; 2) the resetting operation of the FIR-DAC feedback induces a long settling behavior at the beginning of the incremental accumulation. In Ref. [
Figure 15.(Color online) Block diagram of CT IADC in Ref. [
The loop filters in CTDSM can also be effectively used in the CT IADCs. For example, Ref. [
Incremental ADCs comparison and discussion
IEDM, 2019,
| IISW, 2020,
| ISCAS, 2020,
| ISSCC, 2020,
| EDL, 2020,
| JSSC, 2018,
| VLSI, 2021,
| |
---|---|---|---|---|---|---|---|
Sensor type | Multi-gain response | Multi-gain response | Non-linear response | Non-linear response | Low-noise | Low-noise | QIS |
Process | N/A | 45 nm CIS/
| 350 nm CIS | 90 nm CIS/
| 180 nm CIS | 45 nm CIS/
| 45 nm CIS/
|
Pixel array | 64 M | 0.8 M | 0.07 M | 9.2 M | 0.02 M | 8.3 M | 4 M |
Pixel pitch (μm) | N/A | 4 | 15 | 4.86 | NA | 1.1 | 2.2 |
FWC (e-) | 1.2 × 104 | 1.3 × 105 | N/A | N/A | 6.5 × 103 | N/A | 3 × 104 |
Noise (e-) | 1.2 | 4 | N/A | N/A | 0.32 | 0.66 | 0.27 |
DR (dB) | 80 | 90 | 124 | >124 dB | 84.8 | N/A | 100 |
Table 0. Performance summary of the state-of-the-art HDR sensors.
Figure 16.(Color online) State-of-the-art Nyquist ADCs survey published in ISSCC and VLSI[
Pipeline hybrid ADCs
The pipelined concept in analog-to-digital converter can be traced back to the 1960s when Servin from Texas Instruments presented a 1 b/stage pipelined ADC in a patent[
Figure 17.Early pipelined ADC patent with 1 b/stage[
Through the ADC performance survey done by Boris Murmann[
Figure 18.(Color online) ADC survey with Schreier FoM vs. speed.
In recent years, the basic operation of the pipelined ADC has been revisited. Conventionally, each stage (except the last one) has to accomplish three major operations in series, including sampling, quantization, and residue amplification. Ref. [
Another recently proposed technique that changes the nature of conventional pipelined ADCs is to move the architecture in fully continuous-time (CT)[
Going for the hybrid is the next popular option that further pushes the pipelined ADC performance. Benefiting from the outstanding energy efficiency of SAR architecture, the hybridization between the pipeline and SAR ADCs has also become attractive. From 2019 to 2022, various SAR-assisted pipelined (Pipe-SAR) ADCs achieve a top FoMs in their corresponding specification range. In Ref. [
Figure 19.(Color online) ADC survey with energy vs. SNDR.
Besides hardcore Pipe-SAR ADCs, other works[
It is well known that the inter-stage gain error in the pipelined ADCs is circuital and often calls for power-hungry opamp or calibration. Ref. [
Last but not least, the pipelined concept itself is now moving from the classical voltage domain to the time domain. This new thought has been mentioned in Ref. [
Power converters
Many new architectures and emerging applications appeared in recent years in the power converters area. This section will summarize the recent hybrid DC–DC converter topologies, which provide higher power density and higher efficiency at large voltage conversion ratios. Then, we discuss the fast transient response issues of both conventional and hybrid DC–DC converters for point-of-load applications. In the second-half of this section, we discuss the challenges of the two emerging applications: isolated power for harsh environments, and supply modulator for 5G PA.
Hybrid DC–DC converter topologies
With the developments of portable, wearable, and IoT devices, the energy conversion technologies face many new challenges. These applications often require higher power density and efficient space utilization, wider input-output coverages, and the ability to maintain high efficiency over a wide voltage conversion ratio (VCR) range. Actually, there is a compromise among efficiency, power density, and conversion ratio.
Traditional inductive topologies, such as buck and boost converters, can achieve high efficiency with a wide voltage range and a continuous VCR, but require large-size high-quality inductor(s), which leads to low power density. Besides, when the input/output voltage is high, the conduction and switching loss deteriorate. On the other hand, switched-capacitor (SC) converter can achieve high efficiency at a specific VCR only, limited by the charge sharing loss. Even if the adjustable VCR is adopted, the increase of the number of switches will sacrifice power density.
The hybrid architecture converter combines the advantages of inductive and SC topologies. The large inductor can be replaced by a smaller one, while the soft charging of capacitors can alleviate the issue of charge sharing loss. The hybrid architecture provides an effective scheme to realize the favorable trade-off among the efficiency, power density and VCR.
As summarized in
Figure 20.Overview map of hybrid DC–DC topologies and their relevance.
Flying capacitor multi-level topology
FCML topologies can reduce the voltage stress on the switches as well as the voltage ripple on the switching node by adding flying capacitor(s) in the buck topology, and can also realize a higher effective switching frequency (
Hybrid switched-capacitor topology
Hybrid switched-capacitor topology (
A hybrid SC converter based on Dickson topology is proposed in Ref. [
Inductor-first topology
Repositioning the inductor from the output to the input (
A passive-stacked 3rd-order buck (PS3B) converter[
A flying inductor hybrid architecture for USB-C charging is proposed in Ref. [
Dual-path topology
An additional power path is formed by flying capacitors to share the current pressure on the inductor in the dual-path topologies (
A dual-path buck converter topology is presented in Ref. [
Double step-down topology
Double-step down (DSD) topology (
The advantages of DSD topology are analyzed in detail in Ref. [
The comparison of the five different hybrid DC–DC categories is listed in
IEDM, 2019,
| IISW, 2020,
| ISCAS, 2020,
| ISSCC, 2020,
| EDL, 2020,
| JSSC, 2018,
| VLSI, 2021,
| |
---|---|---|---|---|---|---|---|
Sensor type | Multi-gain response | Multi-gain response | Non-linear response | Non-linear response | Low-noise | Low-noise | QIS |
Process | N/A | 45 nm CIS/
| 350 nm CIS | 90 nm CIS/
| 180 nm CIS | 45 nm CIS/
| 45 nm CIS/
|
Pixel array | 64 M | 0.8 M | 0.07 M | 9.2 M | 0.02 M | 8.3 M | 4 M |
Pixel pitch (μm) | N/A | 4 | 15 | 4.86 | NA | 1.1 | 2.2 |
FWC (e-) | 1.2 × 104 | 1.3 × 105 | N/A | N/A | 6.5 × 103 | N/A | 3 × 104 |
Noise (e-) | 1.2 | 4 | N/A | N/A | 0.32 | 0.66 | 0.27 |
DR (dB) | 80 | 90 | 124 | >124 dB | 84.8 | N/A | 100 |
Table 0. Performance summary of the state-of-the-art HDR sensors.
Fast transient DC–DC converters
Besides efficiency and power density, fast transient response is an important property of point-of-load voltage regulator for microprocessors for high-performance computing, which could have a fast load current transient approaching 1 A/ns and would require a dynamic voltage scaling (DVS) speed of 1 V/µs. Low-dropout regulators (LDOs) can provide both fast load transient response and DVS speed, but its efficiency degrades proportionally with the input-output voltage difference. Therefore, the buck DC–DC converter as the 1st-stage of the power delivery system should also have fast transient capability to support the LDOs for higher system efficiency.
As a large inductance is favorable for reducing the inductor current ripple, the maximum transient response speed of a conventional buck converter is limited by the current slew rate of the power inductor (SRL). Also, the transient response can be limited by the controller’s delay. For the hybrid DC–DC converters discussed in the sub-section above, a smaller inductor can be used for higher efficiency and also higher power density, which should be good for fast transient. However, as the voltage across the power inductor in a hybrid topology is also reduced, the SRL would be considerably limited by the lower voltage across the inductor. Recent literatures[
IEDM, 2019,
| IISW, 2020,
| ISCAS, 2020,
| ISSCC, 2020,
| EDL, 2020,
| JSSC, 2018,
| VLSI, 2021,
| |
---|---|---|---|---|---|---|---|
Sensor type | Multi-gain response | Multi-gain response | Non-linear response | Non-linear response | Low-noise | Low-noise | QIS |
Process | N/A | 45 nm CIS/
| 350 nm CIS | 90 nm CIS/
| 180 nm CIS | 45 nm CIS/
| 45 nm CIS/
|
Pixel array | 64 M | 0.8 M | 0.07 M | 9.2 M | 0.02 M | 8.3 M | 4 M |
Pixel pitch (μm) | N/A | 4 | 15 | 4.86 | NA | 1.1 | 2.2 |
FWC (e-) | 1.2 × 104 | 1.3 × 105 | N/A | N/A | 6.5 × 103 | N/A | 3 × 104 |
Noise (e-) | 1.2 | 4 | N/A | N/A | 0.32 | 0.66 | 0.27 |
DR (dB) | 80 | 90 | 124 | >124 dB | 84.8 | N/A | 100 |
Table 0. Performance summary of the state-of-the-art HDR sensors.
The ∆VOUT,Norm should be larger than one if all the ILOAD during the transient response is provided by inductor current IL. The smaller ∆VOUT,Norm indicates a faster controller speed.
Ref. [
Ref. [
Ref. [
Ref. [
Ref. [
Ref. [
Ref. [
Refs. [
Therefore, Ref. [
Ref. [
As a brief summary, recent fast-transient buck converters used small inductors (down to several nH), to increase the SRL. Therefore, they used several tens of MHz fSW to reduce the inductor current ripple and prevents the inductors from saturation. Multiple-phase buck converters require auto phase shedding to extend high efficiency to a wider power range. Subsequently, the VM-based multiple-phase converters need to optimize compensator according to the phase count activated. For the hybrid converters, they may have inherently inferiorSRL. The study for their fast transient performance should be a future hotspot.
Isolated DC–DC converter
Galvanic isolation separates the input and output supplies of a system to allow power and data delivering through an isolation barrier instead of electrical connections. Unlike a non-isolated DC–DC converter that has only one ground, isolated DC–DC converter can avoid the surge and ground shifting problems by adding this isolation between two voltage sides. So isolated DC–DC converter plays a key role in guaranteeing system safety and reliability in harsh industrial environments (e.g. electrical vehicle, communication systems, medical devices, etc.). Some examples include preventing electrical shock to human operators, protecting expensive devices from risk of damage in a high voltage side, and breaking ground loop. In
Figure 21.(Color online) Block diagram of an isolated DC–DC converter.
Figure 22.(Color online) Peak efficiency, maximum output power and EMI performance comparison for the reported isolated DC–DC converters.
Efficiency and power density of isolated DC–DC
To keep improving the efficiency and power density of isolated DC–DC converters, some state-of-the-art efforts have been devoted to meet these challenges recently. Power delivering with isolation barrier can be implemented through capacitive coupling or a transformer. Due to the output power is proportional to isolation capacitance, and its inversely proportional to thickness of dielectric, and thus high-isolation-rate capacitors limit the power capacity[
In order to increase both the output power and the isolation rating, isolated DC–DC converters using micro-transformers have been reported[
In addition, these isolated converters are assembled in a small-outline integrated-circuit (SOIC) package with size of 6 × 10 mm2[
EMI emission of isolated DC–DC
Along with isolated DC–DC converters scaling, those converters above switch currents of several hundred mA at frequencies more than tens of MHz, and thus operation at these high frequency raises concerns about EMI radiated emissions. Some converters use the LC tank oscillator adopted in Ref. [
Recently, low-cost circuit techniques to reduce EMI at the source are demonstrated in Refs. [
In summary, the capacitive isolated DC–DC converters offer remarkable conversion efficiency, while extra devices needed and low-breakdown-voltage capacitive isolation limit the overall package from being further minimized and working in high isolation rating scenarios. The peak efficiency and power density of transformer-based isolated DC–DC converters are constantly refreshed. However, the efficiency in light load condition and EMI performance in heavy load condition are still the main challenges.
Supply modulators for PA
The 5G mobile communication enables up to 100/200 MHz signal bandwidth, which is much faster than 4G long-term-evolution (LTE) communication, however, features a higher peak-to-average power ratio (PAPR) around 10 dB, which significantly reduces the radio-frequency (RF) power amplifiers (PA) efficiency to below 10%. To solve this critical problem, envelope tracking (ET) supply modulator (SM) is the key. The requirements on the ETSM for 5G are extremely challenging, including above several hundred MHz bandwidth, 0.5 to 6 V dynamic output voltage range, a couple of Watts instantaneous output power, and higher than 80% efficiency.
Most supply modulators adopt a hybrid topology composed of a wide-bandwidth low-efficiency linear amplifier in charge of high frequency power and a high-efficiency switching converter taking over low frequency power as shown in
Figure 23.Design directions of supply modulators.
On the topology level, to improve the linear amplifier efficiency, an AC capacitor at its output is added to isolate its DC current and reduce its supply voltage[
Figure 24.(Color online) Comparison of state-of-the-art supply modulators showing efficiency versus bandwidth.
As for switching converters, they are required to have high-efficiency, fast transient response and high voltage rating. Most of the supply modulators are designed to be directly connected to a lithium-ion battery, of which the voltage can range from 2.5 to 4.2 V with a typical value at 3.7 V. However, the output of the supply modulator can range from 0.5 to 6 V for 5G applications. So both step-up and step-down functions are required for the supply modulator. A buck-boost (BB) converter is usually designed in the SM to generate a stable and high voltage VBB[
To support high voltage with good efficiency, low-voltage devices in advanced technologies such as 65 nm can be stacked to replace thick-oxide devices e.g. LDMOS or I/O devices with smaller switching loss[
The second trend is to design a dual-power-line (DPL) buck converter proposed in Refs. [
Both of multi-level and DPL buck have improved the performance. However, when cascaded with a buck-boost converter, the overall structure has lower efficiency and higher cost and volume, compared with a single-stage converter. To solve those problems while still being able to provide both step-up and step-down voltages, a novel buck-boost converter, which is single stage and does not have RHZ, is proposed in Ref. [
As the bandwidth of 5G increases to 200, 300 and even 320 MHz, traditional analog envelope tracking (AET) encounters an almost impossible challenge to achieve such a wide bandwidth with around 5 V voltage rating and a few hundred pF output capacitor. Moreover, the efficiency predicted by the boundary is lower than 75% for 200 MHz. In ISSCC 2022, a new concept — digital envelope tracking (DET) is proposed by Samsung[
In summary, the design of supply modulators for future communications is difficult and challenging but on the other hand it also opens new opportunities and provides new possibilities.
CMOS image sensors and range sensors
The development of CMOS image sensors is in the trends of better performance and diverse functions, including high speed, high dynamic range, 3D imaging and many other aspects. The high speed dynamic vision sensor mimics the biological visual perception mechanism, which converts light intensity information into visual pulse data to quantify high-speed scenes with a low amount of data. High dynamic range image sensor, which improves the detection ability under high light intensity and low light intensity simultaneously. Also, we will discuss the state-of-the-art time-of-flight (ToF) range sensors for distance detection, including direct ToF sensors and indirect ToF sensors, which have the features of low cost, small size and low power consumption.
High speed dynamic vision sensors
Active pixel sensor (APS) quantifies dynamic scenes as a series of images. It enables high frame rate recording with high power consumption. Compared to APS, biological vision system has superior image information perception and processing capabilities. Inspired by its imaging characteristics, researchers proposed the architecture of dynamic vision sensor (DVS), which abandons the concept of frame, to greatly improve the temporal resolution of quantified light intensity. The schematic diagram of DVS pixel is shown in
Figure 25.(a) DVS Pixel circuit diagram[
The photoreceptor logarithmically converts the input photocurrent to the output voltage. Then, the amplifier amplifies the variation of voltage. Finally, the comparator detects the voltage change and triggers an event pulse when it exceeds the threshold voltage. In other words, the intensity change detector circuit encodes the light intensity changes over time into pulse events of different polarities, as shown in
Delbruck’s group proposed the classic DVS architecture[
Ref. [
Researchers have also made improvements to the quality of sensor output event data. As DVS pixel size shrinks, it becomes more susceptible to noise triggering noise events. In Ref. [
However, DVS discards absolute light intensity information which is useful for many computer vision algorithms. Recently, three pioneering works address the need for high-speed object detection and tracking using dynamic event information and object recognition classification using intensity information[
Bionic visual perception combines optoelectronic perception with neuromorphic computing. It achieves high-speed sensing while the pixel structure is complex. The evolution of the event sensor process is shown in
Figure 26.(Color online) The evolution of the event sensor process.
With the advancement of process technology and in-depth research, the pixel size of the event sensor is continuously reduced and the event rate is continuously increased, enabling faster event transmission at higher spatial resolution, as shown in
IEDM, 2019,
| IISW, 2020,
| ISCAS, 2020,
| ISSCC, 2020,
| EDL, 2020,
| JSSC, 2018,
| VLSI, 2021,
| |
---|---|---|---|---|---|---|---|
Sensor type | Multi-gain response | Multi-gain response | Non-linear response | Non-linear response | Low-noise | Low-noise | QIS |
Process | N/A | 45 nm CIS/
| 350 nm CIS | 90 nm CIS/
| 180 nm CIS | 45 nm CIS/
| 45 nm CIS/
|
Pixel array | 64 M | 0.8 M | 0.07 M | 9.2 M | 0.02 M | 8.3 M | 4 M |
Pixel pitch (μm) | N/A | 4 | 15 | 4.86 | NA | 1.1 | 2.2 |
FWC (e-) | 1.2 × 104 | 1.3 × 105 | N/A | N/A | 6.5 × 103 | N/A | 3 × 104 |
Noise (e-) | 1.2 | 4 | N/A | N/A | 0.32 | 0.66 | 0.27 |
DR (dB) | 80 | 90 | 124 | >124 dB | 84.8 | N/A | 100 |
Table 0. Performance summary of the state-of-the-art HDR sensors.
Figure 27.(Color online) Pixel size and event rate of the event sensors.
High dynamic range image sensors
In the IoT era, new vision applications in scientific, security, automotive, and computer vision areas, need to work in real-time under indoor/outdoor, daytime/nighttime, all kinds of scenarios. To achieve this, high dynamic range (HDR) sensors, which has excellent imaging performance under both high and low illumination environments, is required. Dynamic range (DR) is defined as the ratio of the maximum non-saturated incident light intensity to the minimum detectable optical power, and typically, it can be calculated by the full well capacity (FWC) of pixels divided by the noise signal under dark conditions:
Therefore, to implement a HDR sensor, various methods to increase full well capacity and to reduce readout noise have been proposed, as shown in
Figure 28.(Color online) Summary of high dynamic range techniques.
Multi-gain response HDR sensor
The dynamic range of image sensor can be improved by implementing multiple conversion gain (CG) of the pixel, as high gain can provide low noise and high sensitivity, while low gain benefits to larger full well capacity. However, the simplest multiple gain design for the image sensor cannot realize HDR imaging in a single exposure time, and thus they need a complicated post-processing. Therefore, the researchers with new technologies still intend to achieve HDR within a single exposure time, or by finishing the HDR data processing on chip.
Ref. [
In addition to combining limited linear responses, many scholars are also engaged in the research of nonlinear photo-response image sensors, which can be considered as a combination of numerous linear responses. Ref. [
Low-noise HDR sensor
Low-noise design of image sensors is critical for HDR because the noise level decided the minimum detectable light intensity. The correlated multiple sampling technique (CMS) and high CG are useful to suppress the sensor’s noise. The CMS, of which the sample of the pixel readout signal is operated more than one time, is an effective method to suppress the random noise caused by the transistors in pixel, especially the source follower. However, the repeated sample process will occupy a large amount of readout time. High conversion gain, or amplifying the floating diffusion (FD) voltage in pixel is a direct way to suppress the noise in the readout circuits. But they need additional transistors and thus difficult to apply in a small-pitch pixel.
For reducing the readout noise, Ref. [
Quanta image sensor
In recent years, there are many new structures and operation processes of image sensor proposed to achieve HDR, such as quanta image sensor (QIS). A typical QIS integrates up to a few photoelectrons per pixel in one frame. Spatial and temporal oversampling are implemented to achieve a high dynamic range and a high frame rate that are comparable to the ideal CIS operating mode. Ref. [
The performance of state-of-the-art HDR sensors is summarized in
IEDM, 2019,
| IISW, 2020,
| ISCAS, 2020,
| ISSCC, 2020,
| EDL, 2020,
| JSSC, 2018,
| VLSI, 2021,
| |
---|---|---|---|---|---|---|---|
Sensor type | Multi-gain response | Multi-gain response | Non-linear response | Non-linear response | Low-noise | Low-noise | QIS |
Process | N/A | 45 nm CIS/
| 350 nm CIS | 90 nm CIS/
| 180 nm CIS | 45 nm CIS/
| 45 nm CIS/
|
Pixel array | 64 M | 0.8 M | 0.07 M | 9.2 M | 0.02 M | 8.3 M | 4 M |
Pixel pitch (μm) | N/A | 4 | 15 | 4.86 | NA | 1.1 | 2.2 |
FWC (e-) | 1.2 × 104 | 1.3 × 105 | N/A | N/A | 6.5 × 103 | N/A | 3 × 104 |
Noise (e-) | 1.2 | 4 | N/A | N/A | 0.32 | 0.66 | 0.27 |
DR (dB) | 80 | 90 | 124 | >124 dB | 84.8 | N/A | 100 |
Table 0. Performance summary of the state-of-the-art HDR sensors.
Range sensors
Range sensors have shown growing demand in many applications, such as autonomous driving, augmented reality, robotics, and smart homes. Time-of-flight (ToF) sensor, which can be realized in CMOS process, is one of the range sensors with the features of low cost, small size, and low power consumption. There are two types of ToF sensors according to the depth measurement principles: direct ToF (D-ToF) sensor and indirect ToF (I-ToF) sensor.
Figure 29.(Color online) Principles of ToF sensor system.
Direct ToF (D-ToF) sensor
D-ToF sensor directly measures the flight-time of the pulsed light to calculate the depth between the target and the sensor by recording the pulsed light emission time and photon-incidence time using high resolution time-to-digital converter (TDC) and high-gain photodetector. The photodetector is usually implemented with avalanche photodiode (APD) or single-photon avalanche diode (SPAD). As SPAD has characteristics of high sensitivity, fast response speed and low time jitter, it is more commonly used in D-ToF sensors compared with APD. According to the measurement principle of D-ToF sensor, the depth (d) can be calculated by
where t is the flight time of the light and c is the speed of the light. This equation shows that to reach a millimetric depth resolution, the flight time of the light should be measured with picosecond level precision.
Although D-ToF sensor can achieve long detection distance, its lateral resolution is limited. This is because, a large number of on-chip memories and processing units, which include transimpedance amplifier (TIA) or TDC and histogram generating/processing circuits, are usually required by the pixel array to avoid the influence of photon detection probability and dark count rate of SPAD. Furthermore, the power consumption, dynamic range (DR), frame rate and the adaptability with ambient light of the D-ToF sensor still limit its application areas.
To improve the lateral resolution and frame rate, the pixel-wise exposure control and adaptive clocked recharging have been proposed to suppress the maximum power consumption and improve the DR, so that the lateral resolution of D-ToF sensor has been improved to 960 × 960 with 143 dB DR, 90 fps frame rate and 0.37 W power consumption[
The technology trend of the D-ToF sensors are similar to the CMOS image sensors. The early D-ToF sensors realized with front-side illuminated (FSI) CMOS process, have the disadvantages of large pixel size and low lateral resolution[
Indirect ToF (I-ToF) sensor
I-ToF sensor measures the phase shift of the modulated light to indirectly calculate the depth. The phase shift is measured by the demodulation process, in which the reflected light signal is sampled by four clocks with different phases. If the phase shifts between the sampling clock and the emitted signal are set to be 0°, 90°,180° and 270° at four sampling points, respectively. The phase shift ϕ can be calculated by
where S0–S3 represents the sampled signals in four sampling phases. Since the demodulated phase delay has an unambiguous range of 2π, the maximum measurement depth range dR is limited by
I-ToF sensor can achieve higher lateral resolution than D-ToF sensor. This is because the I-ToF sensor can detect the phase shift by performing simple calculations without large volume memories and complex processing units. However, the maximum detection distance of the I-ToF sensor is short because of the limited emitting power of the light source and limited sensitivity of the photodetector. Furthermore, there are two critical problems in I-ToF sensor: motion artifact for moving objects and depth error from background light or multi-user interference.
To suppress the motion artifact, a dynamic pseudo 4-Tap pixel has been proposed to generate a depth image in a single frame, and over-pixel MIM capacitor has been used to achieve background light cancelling over 120 klux[
The technology trend of the I-ToF sensors is similar to the D-ToF sensors. The early I-ToF sensors, implemented with FSI CMOS process, have the shortcomings of large pixel size and low lateral resolution[
To further improve the lateral and depth resolution of D-ToF sensor, the ToF sensors combining both D-ToF and I-ToF methods have been reported recently. By detecting phases for short ranges while creating a sparse depth map with counting photons for long ranges, the lateral resolution has been improved to 1200 × 900 with configurable depth resolution down to 10 cm[
Several ToF sensors combing D-ToF and I-ToF methods proposed in recent years are implemented with FSI CMOS process[
In summary,
IEDM, 2019,
| IISW, 2020,
| ISCAS, 2020,
| ISSCC, 2020,
| EDL, 2020,
| JSSC, 2018,
| VLSI, 2021,
| |
---|---|---|---|---|---|---|---|
Sensor type | Multi-gain response | Multi-gain response | Non-linear response | Non-linear response | Low-noise | Low-noise | QIS |
Process | N/A | 45 nm CIS/
| 350 nm CIS | 90 nm CIS/
| 180 nm CIS | 45 nm CIS/
| 45 nm CIS/
|
Pixel array | 64 M | 0.8 M | 0.07 M | 9.2 M | 0.02 M | 8.3 M | 4 M |
Pixel pitch (μm) | N/A | 4 | 15 | 4.86 | NA | 1.1 | 2.2 |
FWC (e-) | 1.2 × 104 | 1.3 × 105 | N/A | N/A | 6.5 × 103 | N/A | 3 × 104 |
Noise (e-) | 1.2 | 4 | N/A | N/A | 0.32 | 0.66 | 0.27 |
DR (dB) | 80 | 90 | 124 | >124 dB | 84.8 | N/A | 100 |
Table 0. Performance summary of the state-of-the-art HDR sensors.
Figure 30.(Color online) Number of pixels versus the maximum detection distance of ToF sensors.
Emerging directions
This section will be focusing on the emerging technologies and applications. In the recent years, there are two major emerging hot topics: 1) the quantum computing, and 2) the application-specific integrated circuit (ASIC) design for biomedical and/or healthcare applications.
Cryogenic CMOS for qubit
Compare with the classical computing, quantum computing features higher computing speed and parallel computing capability[
Charbon et al.[
The qubit state readout circuit is a key module in the qubit controller. Prabowo et al.[
The research on cryogenic temperature qubit controlling IC is one of the emerging technology direction in the last decade. The reported solution still suffers from its high-power consumption, single control function, and limited capability of multi-qubits controlling. Recent researches are pushing the frontier of cryogenic qubit controller with lower power consumption and higher integration of more complex quantum system controlling functionalities.
Biomedical frontiers
Recent development in advanced electrochemistry materials and low-power circuit technology makes it possible to create super compact sensor system for various applications, i.e., healthcare and scientific researches. Typically a sensor interface with the impedance detection capability is required. Qu et al.[
Advanced imaging technologies have also been applied to realize compact device for biomedical applications. Janget al.[
In addition, ultrasound, light and other energy supply methods and information transmission technology have been introduced into neural interface applications experiments. Yu et al.[
Conclusions
Thanks to the great joint efforts of a large number of Authors, who presented their understanding and insights with their expertise, this paper summarizes the IC design trends in the year of 2022. Although the integrated circuits have been developed for decades, new system architectures and novel circuit topologies/techniques still keep coming out. And people's demands for higher data rate, higher energy efficiency, higher level of integration, smarter and safer electronic devices have not stopped.
Application-specific or domain-specific IC designs are trending in the AI machine learning and biomedical areas. Hybrid conversion topologies are very popular not only for data converters, but also for power converters as well as for sensors. The operation frequencies of the communication ICs range from kHz to mm-wave bands. To arrive at energy-efficient, compact, and robust solutions, the circuit systems heavily depend on semiconductor technologies, electronic devices, packaging, as well as high-quality passive components. Due to limited capacity and capability, we cannot discuss all the interesting and trending IC design topics in this paper. We believe that more promising solutions to the current challenges and more killer applications will appear to keep the IC design area thriving and flourishing. Last but not least, we hope you enjoyed reading this paper and could find this paper useful for your future research and works.
References
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