Fig. 1. Block diagram of the proposed 76~81 GHz quadrature transceiver
Fig. 2. (a) Schematic of the pre-amplifier with a transformer-based gm-boosted network and output power divider, (b) 3D view of the input transformer, and (c) 3D view of the output power divider.
Fig. 3. Simulated results of the gm-boosted single-stage CS amplifier
Fig. 4. (a) Inter-stage serial inductance network, (b) Inter-stage serial-parallel resonating network, and (c) The proposed LC resonating network
Fig. 5. Simulated results of the inter-stage parasitic capacitance elimination network
Fig. 6. (a) The schematic of proposed active mixer, (b) equivalent model of active mixer inter-stage impedance, and (c) noise model of active mixer and the schematic of dynamic current-bleeding.
Fig. 7. Simulated conversion gain of the active mixer using various architectures
Fig. 8. Chip photograph
Fig. 9. Measured S11 of the down-conversion mixer
Fig. 10. Measured CG of the down-conversion mixer
Fig. 11. Measured input P1dB of the down-conversion mixer
Fig. 12. Measured noise figure of the down-conversion mixer
Ref | Tech | Freq/GHz | Conversion Gain/dB | IP1dB/dBm | NF/dB | DC Power /mW | FOM# |
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[4]EL1’ | 90 nm CMOS | 75~85 | 1.5 | -9 | 23.3 | 13 | 0.004 | [5]IMS17’ | 0.18 µm SiGe | 60 | 10 | -23 | 18 | 39.6 | 0.0038 | [6]MWCL14’ | 0.13 µm SiGe | 76.8 | 14.5 | -24.5 | 6.3 | 76 | 0.005 | [7]TDMR16’ | 65 nm CMOS | 65~75 | -1 | -4 | N/A | N/A | N/A | [8]IMS19’ | 90 nm CMOS | 57~67 | 3 | -10 | N/A | 12.7 | N/A | [9]MWCL17’ | 90 nm CMOS | 57~66 | 8 | -7.6 | 13 | 55 | 0.025 | This work | 55 nm CMOS | 76~81 | 4.1 | -6 | 19 | 20* | 0.02 |
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Table 1. 本文正交下混频器测试性能总结及与已报道混频器的性能对比(25 ℃)