Research and design of high voltage radiation hardened lateral diffused metal oxide semiconductor

Fei CHU; Hongzhuan CHEN; Ling PENG; Ying WANG; Jingyi NING

doi:10.11889/j.1000-3436.2022-0035

[1] M Landowski. Design and modeling of radiation hardened lateral power mosfets, 1-25(2011).

[2] J R Schwank, M R Shaneyfelt, D M Fleetwood et al. Radiation effects in MOS oxides. IEEE Transactions on Nuclear Science, 55, 1833-1853(2008).

[3] H L Hughes, J M Benedetto. Radiation effects and hardening of MOS technology: devices and circuits. IEEE Transactions on Nuclear Science, 50, 500-521(2003).

[4] P C Adell, R D Schrimpf, B K Choi et al. Total-dose and single-event effects in switching DC/DC power converters. IEEE Transactions on Nuclear Science, 49, 3217-3221(2002).

[5] P M Shea. Lateral power mosfets hardened against single event radiation effects, 102-115(2011).

[6] P M Shea, Z J Shen. Numerical and experimental investigation of single event effects in SOI lateral power MOSFETs. IEEE Transactions on Nuclear Science, 58, 2739-2747(2011).

[7] Yanfei LI, Jianwei WU, Xiang GU et al. Structure optimization for SEB tolerant enhancement in 30 V NLDMOS. Electronics and Packaging, 18, 36-39(2018).

[8] J L Titus. An updated perspective of single event gate rupture and single event burnout in power MOSFETs. IEEE Transactions on Nuclear Science, 60, 1912-1928(2013).

[9] J R Schwank, V Ferlet-Cavrois, M R Shaneyfelt et al. Radiation effects in SOI technologies. IEEE Transactions on Nuclear Science, 50, 522-538(2003).

[10] Y P Jia, L Peng, H Y Su et al. Effect of grade doping buffer layer on SEE failure in VDMOSFET, 276-279(2016).

[11] P E Dodd, M R Shaneyfelt, B L Draper et al. Development of a radiation-hardened lateral power MOSFET for POL applications. IEEE Transactions on Nuclear Science, 56, 3456-3462(2009).

[12] M Hamlyn, P L Hower, K Warren et al. Transmission line pulse test method for estimating SEB performance of n-channel lateral DMOS power transistors. IEEE Transactions on Nuclear Science, 65, 249-255(2018).

[13] S Liu, M Boden, D A Girdhar et al. Single-event burnout and avalanche characteristics of power DMOSFETs. IEEE Transactions on Nuclear Science, 53, 3379-3385(2006).

[14] S Liu, J L Titus, M Boden. Effect of buffer layer on single-event burnout of power DMOSFETs. IEEE Transactions on Nuclear Science, 54, 2554-2560(2007).