• Journal of Semiconductors
  • Vol. 41, Issue 10, 102404 (2020)
Hao Zhang1, Qiangsheng Cui2, Xu Yan1、3, Jiahui Shi1, and Fujiang Lin1
Author Affiliations
  • 1Micro-/Nano-Electronic System Integration R&D Center (MESIC), University of Science and Technology of China (USTC), Hefei 230026, China
  • 2Hengxin Semitech Co., Ltd., Suzhou 215123, China
  • 3Department of Electrical and Computer Engineering (ECE), National University of Singapore (NUS), Singapore 117583, Singapore
  • show less
    DOI: 10.1088/1674-4926/41/10/102404 Cite this Article
    Hao Zhang, Qiangsheng Cui, Xu Yan, Jiahui Shi, Fujiang Lin. A 0.5–3.0 GHz SP4T RF switch with improved body self-biasing technique in 130-nm SOI CMOS[J]. Journal of Semiconductors, 2020, 41(10): 102404 Copy Citation Text show less
    References

    [1] X Yan, Y Li, Y Chen et al. A LNA-merged RF front-end with digitally assisted technique for gain flatness and input-match compensation. Analog Integr Circuits Signal Process, 101, 219(2019).

    [2] H Zhang, X Yan, J H Shi et al. A 0.5–5.6 GHz inductorless wideband LNA with local active feedback. 2018 IEEE 3rd International Conference on Integrated Circuits and Microsystems (ICICM), 164(2018).

    [3] X Yan, C Chen, L Yang et al. A 0.1–1.1 GHz inductorless differential LNA with double gm -boosting and positive feedback. Analog Integr Circuits Signal Process, 93, 205(2017).

    [4]

    [5] D Im, B K Kim, D K Im et al. A stacked-FET linear SOI CMOS cellular antenna switch with an extremely low-power biasing strategy. IEEE Trans Microw Theory Tech, 63, 1964(2015).

    [6] M Ahn, J Cha, C Cho et al. Ultra low loss and high linearity SPMT antenna switch using SOI CMOS process. 40th Eur Microw Conf, 652(2010).

    [7] A B Joshi, S Lee, Y Y Chen et al. Optimized CMOS-SOI process for high performance RF switches. 2012 IEEE Int SOI Conf SOI, 1(2012).

    [8] K Ben Ali, C Roda Neve, A Gharsallah et al. Ultrawide frequency range crosstalk into standard and trap-rich high resistivity silicon substrates. IEEE Trans Electron Devices, 58, 4258(2011).

    [9] X S Wang, C P Yue. A dual-band SP6T t/r switch in SOI CMOS with 37-dBm P–0.1 dB for GSM/W-CDMA handsets. IEEE Trans Theory Technol, 62, 861(2014).

    [10] T Ohnakado, S Yamakawa, T Murakami et al. 21.5 dBm power-handling 5 GHz transmit/receive CMOS switch realized by voltage division effect of stacked transistor configuration with depletion-layer-extended transistors (DETs). 2003 Symp VLSI Circuits Dig Tech Pap, 1152, 25(2003).

    [11] M Ahn, C H Lee, B S Kim et al. A high-power CMOS switch using A novel adaptive voltage swing distribution method in multistack FETs. IEEE Trans Microw Theory Tech, 56, 849(2008).

    [12] M Ahn, H W Kim, C H Lee et al. A 1.8-GHz 33-dBm P0.1-dB CMOS T/R switch using stacked FETs with feed-forward capacitors in a floated well structure. IEEE Trans Microw Theory Tech, 57, 2661(2009).

    [13] J Cui, L Chen, Y Liu. Monolithic single-pole sixteen-throw T/R switch for next-generation front-end module. IEEE Microw Wirel Compon Lett, 24, 345(2014).

    [14] M C Yeh, Z M Tsai, R C Liu et al. Design and analysis for a miniature CMOS SPDT switch using body-floating technique to improve power performance. IEEE Trans Microw Theory Tech, 54, 31(2006).

    [15]

    [16] Z H Zhang, L Huang, K Yu et al. A novel body self-biased technique for enhanced RF performance of a SP8T antenna switch in partially depleted CMOS-SOI technology. 2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 1(2014).

    [17] H F Xu, K O Kenneth. A 31.3-dBm bulk CMOS T/R switch using stacked transistors with sub-design-rule channel length in floated p-wells. IEEE J Solid-State Circuits, 42, 2528(2007).

    [18] Y C Tseng, W M Huang, D J Monk et al. AC floating body effects and the resultant analog circuit issues in submicron floating body and body-grounded SOI MOSFET's. IEEE Trans Electron Devices, 46, 1685(1999).

    [19] J Cha, M Ahn, C Cho et al. Analysis and design techniques of CMOS charge-pump-based radio-frequency antenna-switch controllers. IEEE Trans Circuits Syst I, 56, 1053(2009).

    [20] H W Zhu, Q L Li, H Sun et al. Ultra low loss and high linearity RF switch using 130 nm SOI CMOS process. 2017 IEEE 12th International Conference on ASIC (ASICON), 698(2017).

    [21] H Guan, H Sun, J L Bao et al. High-performance RF switch in 0.13 μm RF SOI process. J Semicond, 40, 022401(2019).

    Hao Zhang, Qiangsheng Cui, Xu Yan, Jiahui Shi, Fujiang Lin. A 0.5–3.0 GHz SP4T RF switch with improved body self-biasing technique in 130-nm SOI CMOS[J]. Journal of Semiconductors, 2020, 41(10): 102404
    Download Citation