Author Affiliations
1Micro-/Nano-Electronic System Integration R&D Center (MESIC), University of Science and Technology of China (USTC), Hefei 230026, China2Hengxin Semitech Co., Ltd., Suzhou 215123, China3Department of Electrical and Computer Engineering (ECE), National University of Singapore (NUS), Singapore 117583, Singaporeshow less
Fig. 1. The block diagram of the proposed SP4T switch. Schematic of a single switch branch is depicted.
Fig. 2. (Color online) IL and isolation at 1.98 GHz vs stack number.
Fig. 3. Input 0.1-dB compression point at 1.9 GHz vs. stack number.
Fig. 4. (Color online) IL and isolation vs series-FET width.
Fig. 5. Different biasing strategies. (a) Floating body FET biasing. (b) Resistive body-floating biasing. (c) DC-lifting biasing. (d) Proposed body self-biasing strategy using diodes.
Fig. 6. (Color online) IL and isolation of different biasing strategies.
Fig. 7. (Color online) Harmonic level at 1.98 GHz of different biasing strategies.
Fig. 8. Block diagram of the controller.
Fig. 9. (Color online) Micrographs of the fabricated chip and evaluation board.
Fig. 10. (Color online) Measured insertion loss of the SP4T switch.
Fig. 11. (Color online) Measured isolation of the proposed SP4T switch.
Fig. 12. Simulated input power compression point of the SP4T switch.
Fig. 13. Measured input power compression point of the SP4T switch.
Fig. 14. (Color online) Measured 2nd harmonics of the SP4T switch.
Fig. 15. (Color online) Measured 3rd harmonics of the SP4T switch.
Biasing | (a) | (b) | (c) | (d) |
---|
P0.1 dB (dBm)
| 37.3 | 40.2 | 36.7 | 40.1 |
|
Table 1. P0.1 dB at 1.9 GHz of different biasing strategies.
Parameter | Ref. [5]
| Ref. [6]
| Ref. [20]
| Ref. [21]
| This work |
---|
* 1-dB compression point. **Pin = 35 dBm at 900 MHz and 33 dBm at 1.9 GHz. *** including controller. **** frequency not specified.
| SPXT | SP4T | SP4T | SPDT | SPST | SP4T | f (GHz)
| 0.90/1.9 | 0.90/1.9 | 0.90/1.9 | 0.90/1.9 | 0.90/1.9 | Insertion loss (dB) | 0.49/0.70 | 0.30/0.37 | 0.25/0.30 | 0.24/0.34 | 0.27/0.33 | Isolation (dB) | 37/32 | 40/33 | 29/22 | 29/22 | 35/27 | P0.1 dB (dBm)
| 38* | NA | 35* | 36 | 38.5 | 2nd Harmonic (dBc)** | 82/83 | 90/83 | 91/NA | 96**** | 91/96 | 3rd Harmonic (dBc)** | 80/81 | 85/78 | 88/NA | 78**** | 82/83 | Area (mm2)
| 0.98*** | 1.01*** | 0.43 | 0.20 | 0.49*** | Stack number | 10 | NA | 10 | 10 | 9 | Biasing strategy | Improved dc-lifting | RBFT | RBFT | pFET body self-biasing | Diode body self-biasing | Technology | 0.25 μm SOI CMOS
| 0.13 μm SOI CMOS
| 0.13 μm SOI CMOS
| 0.13 μm SOI CMOS
| 0.13 μm SOI CMOS
|
|
Table 2. Comparison of RF switch performance.