Extreme ultraviolet (EUV) lithography is considered to be the most promising technology for fabricating technology nodes of 7 nm and below in high volume manufacturing (HVM). Due to the shrinkage of semiconductor device features and the increase in process complexity, achieving an acceptable yield is challenging. Edge placement error (EPE) quantifies the pattern fidelity of a device structure created in a multi-patterning scheme. It is urgent to reduce EPE to guarantee the proper functioning of semiconductor devices. Therefore, controlling EPE is one of the most serious challenges in the field of multi-patterning and EUV lithography.

EPE is a complex metric, involving error components from various process steps (e.g., lithography and etching steps). It is the combination of critical dimension (CD) errors and overlay errors (see Fig.1(a)). The ratio of each component to the EPE budget changes with the iteration of the logic node (see Fig.1(b)). Stochastic contributions to the EPE budget are increasing rapidly (>50%). Hence, the accurate estimation and measurement of each component of EPE, particularly the stochastic components, are critical to enabling a holistic approach to EPE control and thereby improving the yield. A holistic approach is adopted to optimize the EPE budget (see Fig.2).

This review is organized in five parts. First, we take a broad view of EPE in EUV lithography. Second, we highlight the characteristics peculiar to EUV lithography, considering the optical proximity correction (OPC) and stochastics. Third, we discuss two EPE models, including the optimization flow and the calculation process of EPE from metrology inputs (e.g., CD and overlay). Fourth, we present the metrologies of CD and overlay errors, summarizing the advantages and disadvantages of each method. Finally, we discuss the techniques for EPE.

The typical deep ultraviolet (DUV) immersion lithography works with a transmissive mask, while EUV works with a reflective one (see Fig.4). In addition, the EUV mask is exposed under oblique incidence. Some characteristics such as flare, mask absorber behavior, and mask three-dimensional effects (M3D effects) need to be considered. For instance, M3D effects cause wafer-level deviations from the intended design of an integrated circuit. To address these issues, OPC can be used. The EUV OPC model error contribution of each physical effect is presented in Fig.5(a). Typically, rule-based and model-based approaches are used. Sub-resolution assist features (SRAF) can be used to improve the depth of focus and exposure latitude at a given pitch. In addition, exploring machine learning OPC is also an important tendency. For EUV lithography, due to off-axis illumination and the large ratio between absorber thickness (50‒100 nm) and operating wavelength (13.5 nm), the mask needs rigorous electromagnetic field (EMF) solvers to simulate the light diffraction from the mask. The finite difference time domain (FDTD) method can be used to simulate the 3D masks, but it is computationally expensive and time-consuming. An approximate M3D filter calculation method based on an M3D library and a mask defocus is applied to predict the patterns on wafers.

The energy of EUV (13.5 nm, ~92 eV) is larger than the resist atomic species' electron binding energies, and ionization is the main mechanism. In resist, the electrons can travel farther than 10 nm, which has implications for the understanding of noise, critical dimension uniformity (CDU), and line edge roughness (LER) variations. The stochastic nature of EUV lithography brings many undesirable effects, and it becomes worse when trying to manufacture at high resolution and high throughput. For EUV lithography, local critical dimension uniformity (LCDU) and LER are typically large because of the increased presence of stochastic noise in low doses. Three main approaches to controlling stochastics exist (see Fig.6(a)). The stochastics can be simulated by Monte Carlo models or multivariate Poisson propagation models (MPPM).

For the most advanced nodes, stochastics are generally considered to be the dominant aspect of an EPE budget. It is necessary to explore new methods to properly account for the stochastics in EPE budgets. Mulkens et al. provide a method that is widely applied. It is a computational method that links different EPE budget components. The definition of EPE is shown in Fig.7(a). The calculation process of EPE from various CD and overlay metrology inputs is illustrated in Fig.7(b). The EPE optimization flow (a five-step iterative process) is presented in Fig.7(c). Mack et al. propose a more rigorous, stochastics-aware disposition approach for complementary lithography. By using measurable quantities, this model realizes the accurate prediction of EPE-based failure rates for lot dispositioning. The above two models are reviewed.

With the CD shrinkage, the complex 3D architectures also increase. Worse still, for high NA EUV lithography, due to the reduction in the depth of focus, we apply thinner resist films (<15 nm). It brings a great challenge to conventional CD metrology (e.g., optical CD and CD-SEM). The mechanism, key limits, and challenges of CD metrology are summarized. Computational imaging is a promising technique because of the merits of higher resolution and a larger optical field of view.

Tight and effective overlay control is essential to securing yield. The main contributors to the overlay budget are the scanner, mask, process, and overlay metrology. The overlay optimization flow is illustrated in Fig. 10(b). Optical overlay metrology has been widely adopted for overlay control. Imaging-based overlay (IBO) and diffraction-based overlay (DBO) are the two dominant technologies. The schematic overlay metrology method of DBO is shown in Fig.11(a)‒(e). When the logic design rules are down to 3 nm, on-product overlay (OPO) is becoming the most important factor limiting yields. Overlay error metrology and systems with higher accuracy (sub-nm scale) are in demand. The accuracy limitations of optical overlay metrology promote complementary overlay metrology (e.g., electron beam-based overlay metrology).

Reducing EPE is essential to enabling high yields in manufacturing processes. In this paper, OPC and stochastics in EUV lithography are highlighted. Two models of EPE are reviewed, and the principal components of an EPE budget are systematically discussed. A holistic approach is significant to meet the severe demands of patterning in EPE control. It combines computational mask optimization (e.g., OPC), wafer metrology overlay/CD, co-optimization with other processes (e.g., etch), the high-order actuation capability of DUV, and an EUV scanner. New characterization techniques are critical to providing more accurate descriptions of errors in EUV lithography. Computational imaging is a promising approach by which to increase the resolution of the inspection of masks/chips. Machine learning shows economic potential in EPE analysis. This topic is of significance to the roadmap toward technology nodes of 3 nm and below in the semiconductor industry.