• Microelectronics
  • Vol. 52, Issue 3, 413 (2022)
LI Kai, WANG Lin, ZHANG Weizhe, LIU Bo, ZHANG Jincan, and MENG Qingduan
Author Affiliations
  • [in Chinese]
  • show less
    DOI: 10.13911/j.cnki.1004-3365.210362 Cite this Article
    LI Kai, WANG Lin, ZHANG Weizhe, LIU Bo, ZHANG Jincan, MENG Qingduan. A Low Offset High Speed CMOS Dynamic Comparator for GHz High Frequency Application[J]. Microelectronics, 2022, 52(3): 413 Copy Citation Text show less
    References

    [1] FIEDLER H L, HOEFFLINGER B, DEMMER W, et al. A 5-bit building block for 20 MHz A/D converters [J]. IEEE J Sol Sta Circ, 1981, 16(3): 151-155.

    [2] MIYAHARA M, ASADA Y, PAIK D, et al. A low-noise self-calibrating dynamic comparator for high-speed ADCs [C]// IEEE ASSCC. Fukuoka, Japan. 2008: 269-272.

    [3] SUMANEN L, WALTARI M, HALONEN K. A mismatch insensitive CMOS dynamic comparator for pipeline A/D converters [C]// 7th IEEE ICECS. Jounieh, Lebanon. 2000: 32-35.

    [4] JEON H J, KIM Y B. A low-offset high-speed double-tail dual-rail dynamic latched comparator [C]// Proceed 20th ACM Great Lakes Symp VLSI. Providence, TX, USA. 2010: 45-48.

    [5] GAO J, LI G, LI Q. High-speed low-power common-mode insensitive dynamic comparator [J]. Elec Lett, 2015, 51(2): 134-136.

    [6] SCHINKEL D, MENSINK E, KLUMPERINK E, et al. A double-tail latch-type voltage sense amplifier with 18 ps setup+hold time [C]// IEEE ISSCC. San Francisco, CA, USA. 2007: 314-605.

    [7] BABAYAN-MASHHADI S, LOTFI R. Analysis and design of a low-voltage low-power double-tail comparator [J]. IEEE Trans VLSI Syst, 2013, 22(2): 343-352.

    [9] SOLIS C J, DUCOUDRAY G O. High resolution low power 06 μm CMOS 40 MHz dynamic latch comparator [C]// 53rd IEEE IMSCS. Seattle, WA, USA. 2010: 1045-1048.

    [10] KATYAL V, GEIGER R L, CHEN D J. A new high precision low offset dynamic comparator for high resolution high speed ADCs [C]// IEEE APCCAS. Singapore. 2006: 5-8.

    [11] WORAPISHET A, HUGHES J B, TOUMAZOU C. Double-regenerated switched-current comparator [C]// Proceed 6th IEEE ICECS. Paphos, Cyprus. 1999: 1531-1534.

    [12] RAZAVI B, WOOLEY B A. Design techniques for high-speed, high-resolution comparators [J]. IEEE J Sol Sta Circ, 1992, 27(12): 1916-1926.

    [13] SOLIS C J, DUCOUDRAY G O. High resolution low power 06 μm CMOS 40 MHz dynamic latch comparator [C]// 53rd IEEE IMSCS. 2010: 1045-1048.

    [17] GOLL B, ZIMMERMANN H. A 65 nm CMOS comparator with modified latch to achieve 7 GHz/13 mW at 12 V and 700 MHz/47 μW at 06 V [C]// IEEE ISSCC. San Francisco, CA, USA. 2009: 328-329.

    [18] GHASEMI R, AHMADI A, GHASEMIAN H, et al. A novel 6 GHz/ 573 watt/ 30 ps dynamic comparator with complementary differential input in 65 nm CMOS technology [C]// 27th ICEE. Yazd, Iran. 2019: 236-242.

    [19] KUO B J, CHEN B W, TSAI C M. A 06 V, 13 GHz dynamic comparator with cross-coupled latches [C]// VLSI-DAT. Hsinchu, China. 2015: 1-4.

    [20] KIM J I. A two-step offset calibration in dynamic comparator using body voltage control [J]. IEICE Elec Expr, 2017, 14(21): 20170933.

    [21] BABAYAN-MASHHADI S, SARVAGHAD-MOGHADDAM M. Analysis and design of dynamic comparators in ultra-low supply voltages [C]// 22nd ICEE. Tehran, Iran. 2014: 255-258.

    [22] WANG Y, YAO M, GUO B, et al. A low-power high-speed dynamic comparator with a transconductance-enhanced latching stage [J]. IEEE Access, 2019: 93396-93403.

    LI Kai, WANG Lin, ZHANG Weizhe, LIU Bo, ZHANG Jincan, MENG Qingduan. A Low Offset High Speed CMOS Dynamic Comparator for GHz High Frequency Application[J]. Microelectronics, 2022, 52(3): 413
    Download Citation