A high frequency, high speed, low offset voltage dynamic comparator, which was composed of an improved pre-differential operational amplifier and a differential latch was proposed. The differential pre-amplifier employed a cross-coupling load structure of paired PMOS transistors to increase the common-mode gain as well as to reduce the input offset voltage. The output-stage latch module used a dual-tail current source to suppress common-mode noise, so as to improve the output offset and speedup the signal comparison. A clock-controlled switching transistor was designed to replace the traditional reset control module, so as to optimize the layout area, while constructing a positive feedback loop to further accelerate the circuit resetting and settling of output comparison signal. A 65 nm/12 V standard CMOS process was adopted to implement the circuit design of the proposed dynamic comparator, and the features in terms of delay, offset voltage and power consumption were analyzed and evaluated based on process corner and Monte Carlo simulation by Cadence Spectre tool. The results showed that the average power consumption was 117.1 μW at 12 V power supply voltage and 1 GHz input sampling clock. The maximum output delay at the worst SS process corner simulation was only 1534 ps. The average offset voltage by running 1 000 Monte-Carlo simulations was as low as 153 mV. Compared with other comparators, the proposed dynamic comparator had obvious advantages in the performances of voltage offset and high speed delay.